1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Based on arch/arm/include/asm/tlbflush.h
4 *
5 * Copyright (C) 1999-2003 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8 #ifndef __ASM_TLBFLUSH_H
9 #define __ASM_TLBFLUSH_H
10
11 #ifndef __ASSEMBLY__
12
13 #include <linux/bitfield.h>
14 #include <linux/mm_types.h>
15 #include <linux/sched.h>
16 #include <linux/mmu_notifier.h>
17 #include <asm/cputype.h>
18 #include <asm/mmu.h>
19
20 /*
21 * Raw TLBI operations.
22 *
23 * Where necessary, use the __tlbi() macro to avoid asm()
24 * boilerplate. Drivers and most kernel code should use the TLB
25 * management routines in preference to the macro below.
26 *
27 * The macro can be used as __tlbi(op) or __tlbi(op, arg), depending
28 * on whether a particular TLBI operation takes an argument or
29 * not. The macros handles invoking the asm with or without the
30 * register argument as appropriate.
31 */
32 #define __TLBI_0(op, arg) asm (ARM64_ASM_PREAMBLE \
33 "tlbi " #op "\n" \
34 ALTERNATIVE("nop\n nop", \
35 "dsb ish\n tlbi " #op, \
36 ARM64_WORKAROUND_REPEAT_TLBI, \
37 CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \
38 : : )
39
40 #define __TLBI_1(op, arg) asm (ARM64_ASM_PREAMBLE \
41 "tlbi " #op ", %0\n" \
42 ALTERNATIVE("nop\n nop", \
43 "dsb ish\n tlbi " #op ", %0", \
44 ARM64_WORKAROUND_REPEAT_TLBI, \
45 CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \
46 : : "r" (arg))
47
48 #define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg)
49
50 #define __tlbi(op, ...) __TLBI_N(op, ##__VA_ARGS__, 1, 0)
51
52 #define __tlbi_user(op, arg) do { \
53 if (arm64_kernel_unmapped_at_el0()) \
54 __tlbi(op, (arg) | USER_ASID_FLAG); \
55 } while (0)
56
57 /* This macro creates a properly formatted VA operand for the TLBI */
58 #define __TLBI_VADDR(addr, asid) \
59 ({ \
60 unsigned long __ta = (addr) >> 12; \
61 __ta &= GENMASK_ULL(43, 0); \
62 __ta |= (unsigned long)(asid) << 48; \
63 __ta; \
64 })
65
66 /*
67 * Get translation granule of the system, which is decided by
68 * PAGE_SIZE. Used by TTL.
69 * - 4KB : 1
70 * - 16KB : 2
71 * - 64KB : 3
72 */
73 #define TLBI_TTL_TG_4K 1
74 #define TLBI_TTL_TG_16K 2
75 #define TLBI_TTL_TG_64K 3
76
get_trans_granule(void)77 static inline unsigned long get_trans_granule(void)
78 {
79 switch (PAGE_SIZE) {
80 case SZ_4K:
81 return TLBI_TTL_TG_4K;
82 case SZ_16K:
83 return TLBI_TTL_TG_16K;
84 case SZ_64K:
85 return TLBI_TTL_TG_64K;
86 default:
87 return 0;
88 }
89 }
90
91 /*
92 * Level-based TLBI operations.
93 *
94 * When ARMv8.4-TTL exists, TLBI operations take an additional hint for
95 * the level at which the invalidation must take place. If the level is
96 * wrong, no invalidation may take place. In the case where the level
97 * cannot be easily determined, the value TLBI_TTL_UNKNOWN will perform
98 * a non-hinted invalidation. Any provided level outside the hint range
99 * will also cause fall-back to non-hinted invalidation.
100 *
101 * For Stage-2 invalidation, use the level values provided to that effect
102 * in asm/stage2_pgtable.h.
103 */
104 #define TLBI_TTL_MASK GENMASK_ULL(47, 44)
105
106 #define TLBI_TTL_UNKNOWN INT_MAX
107
108 #define __tlbi_level(op, addr, level) do { \
109 u64 arg = addr; \
110 \
111 if (alternative_has_cap_unlikely(ARM64_HAS_ARMv8_4_TTL) && \
112 level >= 0 && level <= 3) { \
113 u64 ttl = level & 3; \
114 ttl |= get_trans_granule() << 2; \
115 arg &= ~TLBI_TTL_MASK; \
116 arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \
117 } \
118 \
119 __tlbi(op, arg); \
120 } while(0)
121
122 #define __tlbi_user_level(op, arg, level) do { \
123 if (arm64_kernel_unmapped_at_el0()) \
124 __tlbi_level(op, (arg | USER_ASID_FLAG), level); \
125 } while (0)
126
127 /*
128 * This macro creates a properly formatted VA operand for the TLB RANGE. The
129 * value bit assignments are:
130 *
131 * +----------+------+-------+-------+-------+----------------------+
132 * | ASID | TG | SCALE | NUM | TTL | BADDR |
133 * +-----------------+-------+-------+-------+----------------------+
134 * |63 48|47 46|45 44|43 39|38 37|36 0|
135 *
136 * The address range is determined by below formula: [BADDR, BADDR + (NUM + 1) *
137 * 2^(5*SCALE + 1) * PAGESIZE)
138 *
139 * Note that the first argument, baddr, is pre-shifted; If LPA2 is in use, BADDR
140 * holds addr[52:16]. Else BADDR holds page number. See for example ARM DDI
141 * 0487J.a section C5.5.60 "TLBI VAE1IS, TLBI VAE1ISNXS, TLB Invalidate by VA,
142 * EL1, Inner Shareable".
143 *
144 */
145 #define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \
146 ({ \
147 unsigned long __ta = (baddr); \
148 unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \
149 __ta &= GENMASK_ULL(36, 0); \
150 __ta |= __ttl << 37; \
151 __ta |= (unsigned long)(num) << 39; \
152 __ta |= (unsigned long)(scale) << 44; \
153 __ta |= get_trans_granule() << 46; \
154 __ta |= (unsigned long)(asid) << 48; \
155 __ta; \
156 })
157
158 /* These macros are used by the TLBI RANGE feature. */
159 #define __TLBI_RANGE_PAGES(num, scale) \
160 ((unsigned long)((num) + 1) << (5 * (scale) + 1))
161 #define MAX_TLBI_RANGE_PAGES __TLBI_RANGE_PAGES(31, 3)
162
163 /*
164 * Generate 'num' values from -1 to 30 with -1 rejected by the
165 * __flush_tlb_range() loop below.
166 */
167 #define TLBI_RANGE_MASK GENMASK_ULL(4, 0)
168 #define __TLBI_RANGE_NUM(pages, scale) \
169 ((((pages) >> (5 * (scale) + 1)) & TLBI_RANGE_MASK) - 1)
170
171 /*
172 * TLB Invalidation
173 * ================
174 *
175 * This header file implements the low-level TLB invalidation routines
176 * (sometimes referred to as "flushing" in the kernel) for arm64.
177 *
178 * Every invalidation operation uses the following template:
179 *
180 * DSB ISHST // Ensure prior page-table updates have completed
181 * TLBI ... // Invalidate the TLB
182 * DSB ISH // Ensure the TLB invalidation has completed
183 * if (invalidated kernel mappings)
184 * ISB // Discard any instructions fetched from the old mapping
185 *
186 *
187 * The following functions form part of the "core" TLB invalidation API,
188 * as documented in Documentation/core-api/cachetlb.rst:
189 *
190 * flush_tlb_all()
191 * Invalidate the entire TLB (kernel + user) on all CPUs
192 *
193 * flush_tlb_mm(mm)
194 * Invalidate an entire user address space on all CPUs.
195 * The 'mm' argument identifies the ASID to invalidate.
196 *
197 * flush_tlb_range(vma, start, end)
198 * Invalidate the virtual-address range '[start, end)' on all
199 * CPUs for the user address space corresponding to 'vma->mm'.
200 * Note that this operation also invalidates any walk-cache
201 * entries associated with translations for the specified address
202 * range.
203 *
204 * flush_tlb_kernel_range(start, end)
205 * Same as flush_tlb_range(..., start, end), but applies to
206 * kernel mappings rather than a particular user address space.
207 * Whilst not explicitly documented, this function is used when
208 * unmapping pages from vmalloc/io space.
209 *
210 * flush_tlb_page(vma, addr)
211 * Invalidate a single user mapping for address 'addr' in the
212 * address space corresponding to 'vma->mm'. Note that this
213 * operation only invalidates a single, last-level page-table
214 * entry and therefore does not affect any walk-caches.
215 *
216 *
217 * Next, we have some undocumented invalidation routines that you probably
218 * don't want to call unless you know what you're doing:
219 *
220 * local_flush_tlb_all()
221 * Same as flush_tlb_all(), but only applies to the calling CPU.
222 *
223 * __flush_tlb_kernel_pgtable(addr)
224 * Invalidate a single kernel mapping for address 'addr' on all
225 * CPUs, ensuring that any walk-cache entries associated with the
226 * translation are also invalidated.
227 *
228 * __flush_tlb_range(vma, start, end, stride, last_level, tlb_level)
229 * Invalidate the virtual-address range '[start, end)' on all
230 * CPUs for the user address space corresponding to 'vma->mm'.
231 * The invalidation operations are issued at a granularity
232 * determined by 'stride' and only affect any walk-cache entries
233 * if 'last_level' is equal to false. tlb_level is the level at
234 * which the invalidation must take place. If the level is wrong,
235 * no invalidation may take place. In the case where the level
236 * cannot be easily determined, the value TLBI_TTL_UNKNOWN will
237 * perform a non-hinted invalidation.
238 *
239 *
240 * Finally, take a look at asm/tlb.h to see how tlb_flush() is implemented
241 * on top of these routines, since that is our interface to the mmu_gather
242 * API as used by munmap() and friends.
243 */
local_flush_tlb_all(void)244 static inline void local_flush_tlb_all(void)
245 {
246 dsb(nshst);
247 __tlbi(vmalle1);
248 dsb(nsh);
249 isb();
250 }
251
flush_tlb_all(void)252 static inline void flush_tlb_all(void)
253 {
254 dsb(ishst);
255 __tlbi(vmalle1is);
256 dsb(ish);
257 isb();
258 }
259
flush_tlb_mm(struct mm_struct * mm)260 static inline void flush_tlb_mm(struct mm_struct *mm)
261 {
262 unsigned long asid;
263
264 dsb(ishst);
265 asid = __TLBI_VADDR(0, ASID(mm));
266 __tlbi(aside1is, asid);
267 __tlbi_user(aside1is, asid);
268 dsb(ish);
269 mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);
270 }
271
__flush_tlb_page_nosync(struct mm_struct * mm,unsigned long uaddr)272 static inline void __flush_tlb_page_nosync(struct mm_struct *mm,
273 unsigned long uaddr)
274 {
275 unsigned long addr;
276
277 dsb(ishst);
278 addr = __TLBI_VADDR(uaddr, ASID(mm));
279 __tlbi(vale1is, addr);
280 __tlbi_user(vale1is, addr);
281 mmu_notifier_arch_invalidate_secondary_tlbs(mm, uaddr & PAGE_MASK,
282 (uaddr & PAGE_MASK) + PAGE_SIZE);
283 }
284
flush_tlb_page_nosync(struct vm_area_struct * vma,unsigned long uaddr)285 static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
286 unsigned long uaddr)
287 {
288 return __flush_tlb_page_nosync(vma->vm_mm, uaddr);
289 }
290
flush_tlb_page(struct vm_area_struct * vma,unsigned long uaddr)291 static inline void flush_tlb_page(struct vm_area_struct *vma,
292 unsigned long uaddr)
293 {
294 flush_tlb_page_nosync(vma, uaddr);
295 dsb(ish);
296 }
297
arch_tlbbatch_should_defer(struct mm_struct * mm)298 static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm)
299 {
300 /*
301 * TLB flush deferral is not required on systems which are affected by
302 * ARM64_WORKAROUND_REPEAT_TLBI, as __tlbi()/__tlbi_user() implementation
303 * will have two consecutive TLBI instructions with a dsb(ish) in between
304 * defeating the purpose (i.e save overall 'dsb ish' cost).
305 */
306 if (alternative_has_cap_unlikely(ARM64_WORKAROUND_REPEAT_TLBI))
307 return false;
308
309 return true;
310 }
311
arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch * batch,struct mm_struct * mm,unsigned long uaddr)312 static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch,
313 struct mm_struct *mm,
314 unsigned long uaddr)
315 {
316 __flush_tlb_page_nosync(mm, uaddr);
317 }
318
319 /*
320 * If mprotect/munmap/etc occurs during TLB batched flushing, we need to
321 * synchronise all the TLBI issued with a DSB to avoid the race mentioned in
322 * flush_tlb_batched_pending().
323 */
arch_flush_tlb_batched_pending(struct mm_struct * mm)324 static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm)
325 {
326 dsb(ish);
327 }
328
329 /*
330 * To support TLB batched flush for multiple pages unmapping, we only send
331 * the TLBI for each page in arch_tlbbatch_add_pending() and wait for the
332 * completion at the end in arch_tlbbatch_flush(). Since we've already issued
333 * TLBI for each page so only a DSB is needed to synchronise its effect on the
334 * other CPUs.
335 *
336 * This will save the time waiting on DSB comparing issuing a TLBI;DSB sequence
337 * for each page.
338 */
arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch * batch)339 static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
340 {
341 dsb(ish);
342 }
343
344 /*
345 * This is meant to avoid soft lock-ups on large TLB flushing ranges and not
346 * necessarily a performance improvement.
347 */
348 #define MAX_DVM_OPS PTRS_PER_PTE
349
350 /*
351 * __flush_tlb_range_op - Perform TLBI operation upon a range
352 *
353 * @op: TLBI instruction that operates on a range (has 'r' prefix)
354 * @start: The start address of the range
355 * @pages: Range as the number of pages from 'start'
356 * @stride: Flush granularity
357 * @asid: The ASID of the task (0 for IPA instructions)
358 * @tlb_level: Translation Table level hint, if known
359 * @tlbi_user: If 'true', call an additional __tlbi_user()
360 * (typically for user ASIDs). 'flase' for IPA instructions
361 * @lpa2: If 'true', the lpa2 scheme is used as set out below
362 *
363 * When the CPU does not support TLB range operations, flush the TLB
364 * entries one by one at the granularity of 'stride'. If the TLB
365 * range ops are supported, then:
366 *
367 * 1. If FEAT_LPA2 is in use, the start address of a range operation must be
368 * 64KB aligned, so flush pages one by one until the alignment is reached
369 * using the non-range operations. This step is skipped if LPA2 is not in
370 * use.
371 *
372 * 2. The minimum range granularity is decided by 'scale', so multiple range
373 * TLBI operations may be required. Start from scale = 3, flush the largest
374 * possible number of pages ((num+1)*2^(5*scale+1)) that fit into the
375 * requested range, then decrement scale and continue until one or zero pages
376 * are left. We must start from highest scale to ensure 64KB start alignment
377 * is maintained in the LPA2 case.
378 *
379 * 3. If there is 1 page remaining, flush it through non-range operations. Range
380 * operations can only span an even number of pages. We save this for last to
381 * ensure 64KB start alignment is maintained for the LPA2 case.
382 *
383 * Note that certain ranges can be represented by either num = 31 and
384 * scale or num = 0 and scale + 1. The loop below favours the latter
385 * since num is limited to 30 by the __TLBI_RANGE_NUM() macro.
386 */
387 #define __flush_tlb_range_op(op, start, pages, stride, \
388 asid, tlb_level, tlbi_user, lpa2) \
389 do { \
390 int num = 0; \
391 int scale = 3; \
392 int shift = lpa2 ? 16 : PAGE_SHIFT; \
393 unsigned long addr; \
394 \
395 while (pages > 0) { \
396 if (!system_supports_tlb_range() || \
397 pages == 1 || \
398 (lpa2 && start != ALIGN(start, SZ_64K))) { \
399 addr = __TLBI_VADDR(start, asid); \
400 __tlbi_level(op, addr, tlb_level); \
401 if (tlbi_user) \
402 __tlbi_user_level(op, addr, tlb_level); \
403 start += stride; \
404 pages -= stride >> PAGE_SHIFT; \
405 continue; \
406 } \
407 \
408 num = __TLBI_RANGE_NUM(pages, scale); \
409 if (num >= 0) { \
410 addr = __TLBI_VADDR_RANGE(start >> shift, asid, \
411 scale, num, tlb_level); \
412 __tlbi(r##op, addr); \
413 if (tlbi_user) \
414 __tlbi_user(r##op, addr); \
415 start += __TLBI_RANGE_PAGES(num, scale) << PAGE_SHIFT; \
416 pages -= __TLBI_RANGE_PAGES(num, scale); \
417 } \
418 scale--; \
419 } \
420 } while (0)
421
422 #define __flush_s2_tlb_range_op(op, start, pages, stride, tlb_level) \
423 __flush_tlb_range_op(op, start, pages, stride, 0, tlb_level, false, kvm_lpa2_is_enabled());
424
__flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end,unsigned long stride,bool last_level,int tlb_level)425 static inline void __flush_tlb_range(struct vm_area_struct *vma,
426 unsigned long start, unsigned long end,
427 unsigned long stride, bool last_level,
428 int tlb_level)
429 {
430 unsigned long asid, pages;
431
432 start = round_down(start, stride);
433 end = round_up(end, stride);
434 pages = (end - start) >> PAGE_SHIFT;
435
436 /*
437 * When not uses TLB range ops, we can handle up to
438 * (MAX_DVM_OPS - 1) pages;
439 * When uses TLB range ops, we can handle up to
440 * (MAX_TLBI_RANGE_PAGES - 1) pages.
441 */
442 if ((!system_supports_tlb_range() &&
443 (end - start) >= (MAX_DVM_OPS * stride)) ||
444 pages >= MAX_TLBI_RANGE_PAGES) {
445 flush_tlb_mm(vma->vm_mm);
446 return;
447 }
448
449 dsb(ishst);
450 asid = ASID(vma->vm_mm);
451
452 if (last_level)
453 __flush_tlb_range_op(vale1is, start, pages, stride, asid,
454 tlb_level, true, lpa2_is_enabled());
455 else
456 __flush_tlb_range_op(vae1is, start, pages, stride, asid,
457 tlb_level, true, lpa2_is_enabled());
458
459 dsb(ish);
460 mmu_notifier_arch_invalidate_secondary_tlbs(vma->vm_mm, start, end);
461 }
462
flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)463 static inline void flush_tlb_range(struct vm_area_struct *vma,
464 unsigned long start, unsigned long end)
465 {
466 /*
467 * We cannot use leaf-only invalidation here, since we may be invalidating
468 * table entries as part of collapsing hugepages or moving page tables.
469 * Set the tlb_level to TLBI_TTL_UNKNOWN because we can not get enough
470 * information here.
471 */
472 __flush_tlb_range(vma, start, end, PAGE_SIZE, false, TLBI_TTL_UNKNOWN);
473 }
474
flush_tlb_kernel_range(unsigned long start,unsigned long end)475 static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
476 {
477 unsigned long addr;
478
479 if ((end - start) > (MAX_DVM_OPS * PAGE_SIZE)) {
480 flush_tlb_all();
481 return;
482 }
483
484 start = __TLBI_VADDR(start, 0);
485 end = __TLBI_VADDR(end, 0);
486
487 dsb(ishst);
488 for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12))
489 __tlbi(vaale1is, addr);
490 dsb(ish);
491 isb();
492 }
493
494 /*
495 * Used to invalidate the TLB (walk caches) corresponding to intermediate page
496 * table levels (pgd/pud/pmd).
497 */
__flush_tlb_kernel_pgtable(unsigned long kaddr)498 static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr)
499 {
500 unsigned long addr = __TLBI_VADDR(kaddr, 0);
501
502 dsb(ishst);
503 __tlbi(vaae1is, addr);
504 dsb(ish);
505 isb();
506 }
507 #endif
508
509 #endif
510