Lines Matching full:dsb
48 * ins_start_offset will help to store start dword of the dsb
58 * DOC: DSB
60 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
61 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
62 * engine that can be programmed to download the DSB from memory.
65 * faster. DSB Support added from Gen12 Intel graphics based platform.
67 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
70 * DSB HW can support only register writes (both indexed and direct MMIO
71 * writes). There are no registers reads possible with DSB HW engine.
74 /* DSB opcodes. */
94 static bool assert_dsb_has_room(struct intel_dsb *dsb) in assert_dsb_has_room() argument
96 struct intel_crtc *crtc = dsb->crtc; in assert_dsb_has_room()
100 return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2, in assert_dsb_has_room()
101 "[CRTC:%d:%s] DSB %d buffer overflow\n", in assert_dsb_has_room()
102 crtc->base.base.id, crtc->base.name, dsb->id); in assert_dsb_has_room()
105 static void intel_dsb_dump(struct intel_dsb *dsb) in intel_dsb_dump() argument
107 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_dump()
111 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n", in intel_dsb_dump()
112 crtc->base.base.id, crtc->base.name, dsb->id); in intel_dsb_dump()
113 for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4) in intel_dsb_dump()
116 intel_dsb_buffer_read(&dsb->dsb_buf, i), in intel_dsb_dump()
117 intel_dsb_buffer_read(&dsb->dsb_buf, i + 1), in intel_dsb_dump()
118 intel_dsb_buffer_read(&dsb->dsb_buf, i + 2), in intel_dsb_dump()
119 intel_dsb_buffer_read(&dsb->dsb_buf, i + 3)); in intel_dsb_dump()
129 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) in intel_dsb_emit() argument
131 if (!assert_dsb_has_room(dsb)) in intel_dsb_emit()
135 dsb->free_pos = ALIGN(dsb->free_pos, 2); in intel_dsb_emit()
137 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_emit()
139 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, ldw); in intel_dsb_emit()
140 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, udw); in intel_dsb_emit()
143 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, in intel_dsb_prev_ins_is_write() argument
153 if (dsb->free_pos == 0) in intel_dsb_prev_ins_is_write()
156 prev_opcode = intel_dsb_buffer_read(&dsb->dsb_buf, in intel_dsb_prev_ins_is_write()
157 dsb->ins_start_offset + 1) & ~DSB_REG_VALUE_MASK; in intel_dsb_prev_ins_is_write()
158 prev_reg = intel_dsb_buffer_read(&dsb->dsb_buf, in intel_dsb_prev_ins_is_write()
159 dsb->ins_start_offset + 1) & DSB_REG_VALUE_MASK; in intel_dsb_prev_ins_is_write()
164 static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg) in intel_dsb_prev_ins_is_mmio_write() argument
167 return intel_dsb_prev_ins_is_write(dsb, in intel_dsb_prev_ins_is_mmio_write()
173 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) in intel_dsb_prev_ins_is_indexed_write() argument
175 return intel_dsb_prev_ins_is_write(dsb, in intel_dsb_prev_ins_is_indexed_write()
181 * intel_dsb_reg_write() - Emit register wriite to the DSB context
182 * @dsb: DSB context
187 * buffer of DSB.
189 void intel_dsb_reg_write(struct intel_dsb *dsb, in intel_dsb_reg_write() argument
205 * As every instruction is 8 byte aligned the index of dsb instruction in intel_dsb_reg_write()
210 if (!intel_dsb_prev_ins_is_mmio_write(dsb, reg) && in intel_dsb_reg_write()
211 !intel_dsb_prev_ins_is_indexed_write(dsb, reg)) { in intel_dsb_reg_write()
212 intel_dsb_emit(dsb, val, in intel_dsb_reg_write()
217 if (!assert_dsb_has_room(dsb)) in intel_dsb_reg_write()
221 if (intel_dsb_prev_ins_is_mmio_write(dsb, reg)) { in intel_dsb_reg_write()
222 u32 prev_val = intel_dsb_buffer_read(&dsb->dsb_buf, in intel_dsb_reg_write()
223 dsb->ins_start_offset + 0); in intel_dsb_reg_write()
225 intel_dsb_buffer_write(&dsb->dsb_buf, in intel_dsb_reg_write()
226 dsb->ins_start_offset + 0, 1); /* count */ in intel_dsb_reg_write()
227 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 1, in intel_dsb_reg_write()
230 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 2, prev_val); in intel_dsb_reg_write()
232 dsb->free_pos++; in intel_dsb_reg_write()
235 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val); in intel_dsb_reg_write()
237 old_val = intel_dsb_buffer_read(&dsb->dsb_buf, dsb->ins_start_offset); in intel_dsb_reg_write()
238 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset, old_val + 1); in intel_dsb_reg_write()
241 if (dsb->free_pos & 0x1) in intel_dsb_reg_write()
242 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0); in intel_dsb_reg_write()
255 void intel_dsb_reg_write_masked(struct intel_dsb *dsb, in intel_dsb_reg_write_masked() argument
258 intel_dsb_emit(dsb, val, in intel_dsb_reg_write_masked()
264 void intel_dsb_noop(struct intel_dsb *dsb, int count) in intel_dsb_noop() argument
269 intel_dsb_emit(dsb, 0, in intel_dsb_noop()
273 void intel_dsb_nonpost_start(struct intel_dsb *dsb) in intel_dsb_nonpost_start() argument
275 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_nonpost_start()
278 intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id), in intel_dsb_nonpost_start()
280 intel_dsb_noop(dsb, 4); in intel_dsb_nonpost_start()
283 void intel_dsb_nonpost_end(struct intel_dsb *dsb) in intel_dsb_nonpost_end() argument
285 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_nonpost_end()
288 intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id), in intel_dsb_nonpost_end()
290 intel_dsb_noop(dsb, 4); in intel_dsb_nonpost_end()
293 static void intel_dsb_align_tail(struct intel_dsb *dsb) in intel_dsb_align_tail() argument
297 tail = dsb->free_pos * 4; in intel_dsb_align_tail()
301 intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, in intel_dsb_align_tail()
304 dsb->free_pos = aligned_tail / 4; in intel_dsb_align_tail()
307 void intel_dsb_finish(struct intel_dsb *dsb) in intel_dsb_finish() argument
309 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_finish()
312 * DSB_FORCE_DEWAKE remains active even after DSB is in intel_dsb_finish()
316 intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id), in intel_dsb_finish()
319 intel_dsb_align_tail(dsb); in intel_dsb_finish()
321 intel_dsb_buffer_flush_map(&dsb->dsb_buf); in intel_dsb_finish()
343 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, in _intel_dsb_commit() argument
346 struct intel_crtc *crtc = dsb->crtc; in _intel_dsb_commit()
351 tail = dsb->free_pos * 4; in _intel_dsb_commit()
355 if (is_dsb_busy(dev_priv, pipe, dsb->id)) { in _intel_dsb_commit()
356 drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n", in _intel_dsb_commit()
357 crtc->base.base.id, crtc->base.name, dsb->id); in _intel_dsb_commit()
361 intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), in _intel_dsb_commit()
364 intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id), in _intel_dsb_commit()
365 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); in _intel_dsb_commit()
372 intel_de_write_fw(dev_priv, DSB_PMCTRL(pipe, dsb->id), in _intel_dsb_commit()
381 intel_de_write_fw(dev_priv, DSB_PMCTRL_2(pipe, dsb->id), in _intel_dsb_commit()
386 intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id), in _intel_dsb_commit()
387 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); in _intel_dsb_commit()
391 * intel_dsb_commit() - Trigger workload execution of DSB.
392 * @dsb: DSB context
395 * This function is used to do actual write to hardware using DSB.
397 void intel_dsb_commit(struct intel_dsb *dsb, in intel_dsb_commit() argument
400 _intel_dsb_commit(dsb, in intel_dsb_commit()
402 wait_for_vblank ? dsb->dewake_scanline : -1); in intel_dsb_commit()
405 void intel_dsb_wait(struct intel_dsb *dsb) in intel_dsb_wait() argument
407 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait()
411 if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { in intel_dsb_wait()
412 u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); in intel_dsb_wait()
414 intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), in intel_dsb_wait()
418 "[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n", in intel_dsb_wait()
419 crtc->base.base.id, crtc->base.name, dsb->id, in intel_dsb_wait()
420 intel_de_read_fw(dev_priv, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset, in intel_dsb_wait()
421 intel_de_read_fw(dev_priv, DSB_HEAD(pipe, dsb->id)) - offset, in intel_dsb_wait()
422 intel_de_read_fw(dev_priv, DSB_TAIL(pipe, dsb->id)) - offset); in intel_dsb_wait()
424 intel_dsb_dump(dsb); in intel_dsb_wait()
428 dsb->free_pos = 0; in intel_dsb_wait()
429 dsb->ins_start_offset = 0; in intel_dsb_wait()
430 intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0); in intel_dsb_wait()
434 * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
438 * This function prepare the command buffer which is used to store dsb
442 * DSB context, NULL on failure
450 struct intel_dsb *dsb; in intel_dsb_prepare() local
456 dsb = kzalloc(sizeof(*dsb), GFP_KERNEL); in intel_dsb_prepare()
457 if (!dsb) in intel_dsb_prepare()
465 if (!intel_dsb_buffer_create(crtc, &dsb->dsb_buf, size)) in intel_dsb_prepare()
470 dsb->id = DSB1; in intel_dsb_prepare()
471 dsb->crtc = crtc; in intel_dsb_prepare()
472 dsb->size = size / 4; /* in dwords */ in intel_dsb_prepare()
473 dsb->free_pos = 0; in intel_dsb_prepare()
474 dsb->ins_start_offset = 0; in intel_dsb_prepare()
475 dsb->dewake_scanline = intel_dsb_dewake_scanline(crtc_state); in intel_dsb_prepare()
477 return dsb; in intel_dsb_prepare()
481 kfree(dsb); in intel_dsb_prepare()
484 … "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n", in intel_dsb_prepare()
491 * intel_dsb_cleanup() - To cleanup DSB context.
492 * @dsb: DSB context
494 * This function cleanup the DSB context by unpinning and releasing
497 void intel_dsb_cleanup(struct intel_dsb *dsb) in intel_dsb_cleanup() argument
499 intel_dsb_buffer_cleanup(&dsb->dsb_buf); in intel_dsb_cleanup()
500 kfree(dsb); in intel_dsb_cleanup()