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/linux-5.10/drivers/gpu/drm/i915/gt/
Dgen2_engine_cs.c17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
32 *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; in gen2_emit_flush()
34 *cs++ = cmd; in gen2_emit_flush()
[all …]
Dgen6_engine_cs.c31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
59 u32 *cs; in gen6_emit_post_sync_nonzero_flush() local
61 cs = intel_ring_begin(rq, 6); in gen6_emit_post_sync_nonzero_flush()
62 if (IS_ERR(cs)) in gen6_emit_post_sync_nonzero_flush()
63 return PTR_ERR(cs); in gen6_emit_post_sync_nonzero_flush()
65 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
66 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; in gen6_emit_post_sync_nonzero_flush()
67 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; in gen6_emit_post_sync_nonzero_flush()
68 *cs++ = 0; /* low dword */ in gen6_emit_post_sync_nonzero_flush()
69 *cs++ = 0; /* high dword */ in gen6_emit_post_sync_nonzero_flush()
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Dgen7_renderclear.c13 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
82 static u32 batch_offset(const struct batch_chunk *bc, u32 *cs) in batch_offset() argument
84 return (cs - bc->start) * sizeof(*bc->start) + bc->offset; in batch_offset()
128 u32 *cs = batch_alloc_items(state, 32, 8); in gen7_fill_surface_state() local
129 u32 offset = batch_offset(state, cs); in gen7_fill_surface_state()
135 *cs++ = SURFACE_2D << 29 | in gen7_fill_surface_state()
139 *cs++ = batch_addr(state) + dst_offset; in gen7_fill_surface_state()
141 *cs++ = ((surface_h / 4 - 1) << 16) | (surface_w / 4 - 1); in gen7_fill_surface_state()
142 *cs++ = surface_w; in gen7_fill_surface_state()
143 *cs++ = 0; in gen7_fill_surface_state()
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/linux-5.10/kernel/time/
Dclocksource.c119 static void __clocksource_change_rating(struct clocksource *cs, int rating);
145 static void __clocksource_unstable(struct clocksource *cs) in __clocksource_unstable() argument
147 cs->flags &= ~(CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_WATCHDOG); in __clocksource_unstable()
148 cs->flags |= CLOCK_SOURCE_UNSTABLE; in __clocksource_unstable()
154 if (list_empty(&cs->list)) { in __clocksource_unstable()
155 cs->rating = 0; in __clocksource_unstable()
159 if (cs->mark_unstable) in __clocksource_unstable()
160 cs->mark_unstable(cs); in __clocksource_unstable()
169 * @cs: clocksource to be marked unstable
174 void clocksource_mark_unstable(struct clocksource *cs) in clocksource_mark_unstable() argument
[all …]
/linux-5.10/drivers/misc/habanalabs/common/
Dcommand_submission.c49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
59 "CS 0x%llx type %d finished, sob_id: %d, sob_val: 0x%x\n", in hl_fence_release()
66 * A signal CS can get completion while the corresponding wait in hl_fence_release()
67 * for signal CS is on its way to the PQ. The wait for signal CS in hl_fence_release()
68 * will get stuck if the signal CS incremented the SOB to its in hl_fence_release()
72 * 1. The wait for signal CS must get a ref for the signal CS as in hl_fence_release()
76 * 2. Signal/Wait for signal CS will decrement the SOB refcnt in hl_fence_release()
78 * These two measures guarantee that the wait for signal CS will in hl_fence_release()
79 * reset the SOB upon completion rather than the signal CS and in hl_fence_release()
108 static void cs_get(struct hl_cs *cs) in cs_get() argument
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/linux-5.10/drivers/scsi/
Dmyrs.c104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
108 union myrs_cmd_mbox *next_mbox = cs->next_cmd_mbox; in myrs_qcmd()
110 cs->write_cmd_mbox(next_mbox, mbox); in myrs_qcmd()
112 if (cs->prev_cmd_mbox1->words[0] == 0 || in myrs_qcmd()
113 cs->prev_cmd_mbox2->words[0] == 0) in myrs_qcmd()
114 cs->get_cmd_mbox(base); in myrs_qcmd()
116 cs->prev_cmd_mbox2 = cs->prev_cmd_mbox1; in myrs_qcmd()
117 cs->prev_cmd_mbox1 = next_mbox; in myrs_qcmd()
119 if (++next_mbox > cs->last_cmd_mbox) in myrs_qcmd()
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/linux-5.10/drivers/memory/
Dstm32-fmc2-ebi.c170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
174 int cs, u32 setup);
179 int cs) in stm32_fmc2_ebi_check_mux() argument
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
193 int cs) in stm32_fmc2_ebi_check_waitcfg() argument
197 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_waitcfg()
207 int cs) in stm32_fmc2_ebi_check_sync_trans() argument
211 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_sync_trans()
221 int cs) in stm32_fmc2_ebi_check_async_trans() argument
[all …]
Domap-gpmc.c203 /* Structure to save gpmc cs context */
263 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
267 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
271 static u32 gpmc_cs_read_reg(int cs, int idx) in gpmc_cs_read_reg() argument
275 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_read_reg()
292 * @cs: Chip Select Region.
295 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
298 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) in gpmc_get_clk_period() argument
307 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); in gpmc_get_clk_period()
320 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, in gpmc_ns_to_clk_ticks() argument
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/linux-5.10/drivers/mfd/
Datmel-smc.c15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
79 * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
81 * @conf: SMC CS conf descriptor
121 * atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a
123 * @conf: SMC CS conf descriptor
160 * atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a
162 * @conf: SMC CS conf descriptor
199 * atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a
201 * @conf: SMC CS conf descriptor
[all …]
/linux-5.10/kernel/cgroup/
Dcpuset.c203 static inline struct cpuset *parent_cs(struct cpuset *cs) in parent_cs() argument
205 return css_cs(cs->css.parent); in parent_cs()
221 static inline bool is_cpuset_online(struct cpuset *cs) in is_cpuset_online() argument
223 return test_bit(CS_ONLINE, &cs->flags) && !css_is_dying(&cs->css); in is_cpuset_online()
226 static inline int is_cpu_exclusive(const struct cpuset *cs) in is_cpu_exclusive() argument
228 return test_bit(CS_CPU_EXCLUSIVE, &cs->flags); in is_cpu_exclusive()
231 static inline int is_mem_exclusive(const struct cpuset *cs) in is_mem_exclusive() argument
233 return test_bit(CS_MEM_EXCLUSIVE, &cs->flags); in is_mem_exclusive()
236 static inline int is_mem_hardwall(const struct cpuset *cs) in is_mem_hardwall() argument
238 return test_bit(CS_MEM_HARDWALL, &cs->flags); in is_mem_hardwall()
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/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt34 - CS-specific partition/range. If continuous, must be
38 - control partition which is common for all CS
56 Child chip-select (cs) nodes contain the memory devices nodes connected to
60 Required child cs node properties:
73 - ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
79 Optional child cs node properties:
81 - ti,cs-bus-width: width of the asynchronous device's data bus
84 - ti,cs-select-strobe-mode: enable/disable select strobe mode
89 - ti,cs-extended-wait-mode: enable/disable extended wait mode
95 - ti,cs-min-turnaround-ns: minimum turn around time, ns
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Dst,stm32-fmc2-ebi.yaml56 st,fmc2-ebi-cs-transaction-type:
75 st,fmc2-ebi-cs-cclk-enable:
82 st,fmc2-ebi-cs-mux-enable:
88 st,fmc2-ebi-cs-buswidth:
94 st,fmc2-ebi-cs-waitpol-high:
99 st,fmc2-ebi-cs-waitcfg-enable:
106 st,fmc2-ebi-cs-wait-enable:
112 st,fmc2-ebi-cs-asyncwait-enable:
118 st,fmc2-ebi-cs-cpsize:
126 st,fmc2-ebi-cs-byte-lane-setup-ns:
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/linux-5.10/tools/perf/util/
Dcomm.c22 static struct comm_str *comm_str__get(struct comm_str *cs) in comm_str__get() argument
24 if (cs && refcount_inc_not_zero(&cs->refcnt)) in comm_str__get()
25 return cs; in comm_str__get()
30 static void comm_str__put(struct comm_str *cs) in comm_str__put() argument
32 if (cs && refcount_dec_and_test(&cs->refcnt)) { in comm_str__put()
34 rb_erase(&cs->rb_node, &comm_str_root); in comm_str__put()
36 zfree(&cs->str); in comm_str__put()
37 free(cs); in comm_str__put()
43 struct comm_str *cs; in comm_str__alloc() local
45 cs = zalloc(sizeof(*cs)); in comm_str__alloc()
[all …]
/linux-5.10/fs/fuse/
Ddev.c664 static void fuse_copy_init(struct fuse_copy_state *cs, int write, in fuse_copy_init() argument
667 memset(cs, 0, sizeof(*cs)); in fuse_copy_init()
668 cs->write = write; in fuse_copy_init()
669 cs->iter = iter; in fuse_copy_init()
673 static void fuse_copy_finish(struct fuse_copy_state *cs) in fuse_copy_finish() argument
675 if (cs->currbuf) { in fuse_copy_finish()
676 struct pipe_buffer *buf = cs->currbuf; in fuse_copy_finish()
678 if (cs->write) in fuse_copy_finish()
679 buf->len = PAGE_SIZE - cs->len; in fuse_copy_finish()
680 cs->currbuf = NULL; in fuse_copy_finish()
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/linux-5.10/arch/mips/bcm63xx/
Dcs.c24 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
26 if (cs > 6) in is_valid_cs()
35 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) in bcm63xx_set_cs_base() argument
40 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
55 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
66 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, in bcm63xx_set_cs_timing() argument
72 if (!is_valid_cs(cs)) in bcm63xx_set_cs_timing()
76 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
83 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
94 int bcm63xx_set_cs_param(unsigned int cs, u32 params) in bcm63xx_set_cs_param() argument
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/linux-5.10/arch/m68k/include/asm/
Dm5307sim.h51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
59 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
60 #define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
61 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
62 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
[all …]
/linux-5.10/include/linux/mfd/syscon/
Datmel-smc.h18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
26 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
32 #define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc) argument
[all …]
/linux-5.10/net/ceph/
Dstring_table.c13 struct ceph_string *cs, *exist; in ceph_find_or_create_string() local
40 cs = kmalloc(sizeof(*cs) + len + 1, GFP_NOFS); in ceph_find_or_create_string()
41 if (!cs) in ceph_find_or_create_string()
44 kref_init(&cs->kref); in ceph_find_or_create_string()
45 cs->len = len; in ceph_find_or_create_string()
46 memcpy(cs->str, str, len); in ceph_find_or_create_string()
47 cs->str[len] = 0; in ceph_find_or_create_string()
68 rb_link_node(&cs->node, parent, p); in ceph_find_or_create_string()
69 rb_insert_color(&cs->node, &string_tree); in ceph_find_or_create_string()
80 kfree(cs); in ceph_find_or_create_string()
[all …]
/linux-5.10/arch/mips/include/asm/netlogic/xlr/
Dflash.h37 #define FLASH_CSBASE_ADDR(cs) (cs) argument
38 #define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) argument
39 #define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) argument
40 #define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) argument
41 #define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) argument
48 #define FLASH_NAND_CLE(cs) (0x90 + (cs)) argument
49 #define FLASH_NAND_ALE(cs) (0xa0 + (cs)) argument
/linux-5.10/drivers/clocksource/
Dtimer-pistachio.c51 struct clocksource cs; member
56 #define to_pistachio_clocksource(cs) \ argument
57 container_of(cs, struct pistachio_clocksource, cs)
71 pistachio_clocksource_read_cycles(struct clocksource *cs) in pistachio_clocksource_read_cycles() argument
73 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles()
92 return pistachio_clocksource_read_cycles(&pcs_gpt.cs); in pistachio_read_sched_clock()
95 static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx, in pistachio_clksrc_set_mode() argument
98 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode()
110 static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx) in pistachio_clksrc_enable() argument
112 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable()
[all …]
/linux-5.10/drivers/spi/
Dspi-fsl-spi.c92 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_change_mode() local
97 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) in fsl_spi_change_mode()
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); in fsl_spi_change_mode()
110 mpc8xxx_spi_write_reg(mode, cs->hw_mode); in fsl_spi_change_mode()
119 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_chipselect() local
129 mpc8xxx_spi->rx_shift = cs->rx_shift; in fsl_spi_chipselect()
130 mpc8xxx_spi->tx_shift = cs->tx_shift; in fsl_spi_chipselect()
131 mpc8xxx_spi->get_rx = cs->get_rx; in fsl_spi_chipselect()
132 mpc8xxx_spi->get_tx = cs->get_tx; in fsl_spi_chipselect()
175 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, in mspi_apply_cpu_mode_quirks() argument
[all …]
/linux-5.10/sound/core/
Dpcm_iec958.c13 u8 *cs, size_t len) in create_iec958_consumer() argument
69 memset(cs, 0, len); in create_iec958_consumer()
71 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in create_iec958_consumer()
72 cs[1] = IEC958_AES1_CON_GENERAL; in create_iec958_consumer()
73 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; in create_iec958_consumer()
74 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | fs; in create_iec958_consumer()
77 cs[4] = ws; in create_iec958_consumer()
85 * @cs: channel status buffer, at least four bytes
88 * Create the consumer format channel status data in @cs of maximum size
95 int snd_pcm_create_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs, in snd_pcm_create_iec958_consumer() argument
[all …]
/linux-5.10/drivers/staging/kpc2000/
Dkpc2000_spi.c126 unsigned int cs : 4; /* Chip Select */ member
163 kp_spi_read_reg(struct kp_spi_controller_state *cs, int idx) in kp_spi_read_reg() argument
165 u64 __iomem *addr = cs->base; in kp_spi_read_reg()
168 if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0)) in kp_spi_read_reg()
169 return cs->conf_cache; in kp_spi_read_reg()
175 kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val) in kp_spi_write_reg() argument
177 u64 __iomem *addr = cs->base; in kp_spi_write_reg()
182 cs->conf_cache = val; in kp_spi_write_reg()
186 kp_spi_wait_for_reg_bit(struct kp_spi_controller_state *cs, int idx, in kp_spi_wait_for_reg_bit() argument
192 while (!(kp_spi_read_reg(cs, idx) & bit)) { in kp_spi_wait_for_reg_bit()
[all …]
/linux-5.10/Documentation/ABI/testing/
Dsysfs-kernel-slab4 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
16 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
25 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
34 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
45 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
56 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
68 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
79 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
90 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
102 Contact: Pekka Enberg <penberg@cs.helsinki.fi>,
[all …]
/linux-5.10/drivers/gpu/drm/i915/selftests/
Di915_perf.c157 u32 *cs; in write_timestamp() local
160 cs = intel_ring_begin(rq, 6); in write_timestamp()
161 if (IS_ERR(cs)) in write_timestamp()
162 return PTR_ERR(cs); in write_timestamp()
168 *cs++ = GFX_OP_PIPE_CONTROL(len); in write_timestamp()
169 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | in write_timestamp()
172 *cs++ = slot * sizeof(u32); in write_timestamp()
173 *cs++ = 0; in write_timestamp()
174 *cs++ = 0; in write_timestamp()
175 *cs++ = 0; in write_timestamp()
[all …]

12345678910>>...70