| /qemu/hw/tricore/ |
| H A D | tc27x_soc.c | 105 make_ram(&s->cpu0mem.dspr, "CPU0.DSPR", in tc27x_soc_init_memory_mapping()
107 make_ram(&s->cpu0mem.pspr, "CPU0.PSPR", in tc27x_soc_init_memory_mapping()
137 make_ram(&s->cpu0mem.pcache, "CPU0.PCACHE", in tc27x_soc_init_memory_mapping()
139 make_ram(&s->cpu0mem.ptag, "CPU0.PTAG", in tc27x_soc_init_memory_mapping()
143 * TriCore QEMU executes CPU0 only, thus it is sufficient to map in tc27x_soc_init_memory_mapping()
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| /qemu/tests/functional/ |
| H A D | test_x86_64_hotplug_cpu.py | 44 'cd /sys/devices/system/cpu/cpu0',
45 'cpu0#')
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| H A D | test_s390x_topology.py | 237 ' syspath="/sys/devices/system/cpu/cpu0/polarization"',
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| /qemu/hw/cpu/ |
| H A D | a9mpcore.c | 56 CPUState *cpu0; in a9mp_priv_realize() local
64 cpu0 = qemu_get_cpu(0); in a9mp_priv_realize()
65 cpuobj = OBJECT(cpu0); in a9mp_priv_realize()
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| /qemu/qapi/ |
| H A D | misc-i386.json | 194 # @cpu0-id: Unique ID of CPU0 (base64 encoded) (since 7.1)
206 'cpu0-id': 'str',
228 # "cpu0-id": "2lvmGwo+...61iEinw==",
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| /qemu/include/hw/arm/ |
| H A D | armsse.h | 56 * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
57 * SSE-200 both are present; CPU0 in an SSE-200 has neither.
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| /qemu/tests/qtest/ |
| H A D | test-x86-cpuid-compat.c | 12 QDict *cpu0; in get_cpu0_qom_path() local
19 cpu0 = qobject_to(QDict, qlist_peek(ret)); in get_cpu0_qom_path()
20 path = g_strdup(qdict_get_str(cpu0, "qom-path")); in get_cpu0_qom_path()
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| /qemu/include/hw/xen/interface/hvm/ |
| H A D | params.h | 34 * How should CPU0 event-channel notifications be delivered?
36 * If val == 0 then CPU0 event-channel notifications are not delivered.
|
| /qemu/hw/alpha/ |
| H A D | typhoon.c | 114 /* DIM0: Device Interrupt Mask Register, CPU0. */ in cchip_read()
122 /* DIR0: Device Interrupt Request Register, CPU0. */ in cchip_read()
139 /* IIC0: Interval Ignore Count Register, CPU0. */ in cchip_read()
377 /* DIM: Device Interrupt Mask Register, CPU0. */ in cchip_write()
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| /qemu/docs/system/arm/ |
| H A D | mps2.rst | 71 CPU0, and the second UART is accessible only by CPU1. The
|
| /qemu/docs/system/ |
| H A D | generic-loader.rst | 107 An example of loading an ELF file which CPU0 will boot is shown below::
|
| /qemu/hw/arm/ |
| H A D | musca.c | 385 * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. in musca_init()
|
| H A D | fsl-imx6ul.c | 38 object_initialize_child(obj, "cpu0", &s->cpu, in fsl_imx6ul_init()
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| H A D | armsse.c | 605 sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */ in armsse_sys_config_value()
1021 * start CPU0 and leave CPU1 powered off, we hard-code that in in armsse_realize()
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| /qemu/hw/ppc/ |
| H A D | spapr_cpu_core.c | 315 * All CPUs start halted. CPU0 is unhalted from the machine level reset code in spapr_create_vcpu()
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| /qemu/include/hw/xen/interface/ |
| H A D | arch-arm.h | 128 * HYPERVISOR_vcpu_op sub-op VCPUOP_register_vcpu_info, including cpu0
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| /qemu/hw/hppa/ |
| H A D | machine.c | 312 cpu[0], "cpu0-io-rtc", 2 * sizeof(uint64_t)); in machine_HP_common_init_cpus()
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| /qemu/tests/unit/ |
| H A D | test-qga.c | 1120 if (!access("/sys/devices/system/cpu/cpu0", F_OK)) { in main()
|
| /qemu/accel/kvm/ |
| H A D | kvm-all.c | 821 * CPU0 CPU1 CPU2 in dirty_gfn_set_collected()
831 * The synchronization goes from CPU2 to CPU0 to CPU1. in dirty_gfn_set_collected()
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| /qemu/hw/i386/kvm/ |
| H A D | xen_evtchn.c | 320 * signalling CPU0's events via GSI or PCI INTx instead of the in xen_evtchn_create()
|