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/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c88 #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
89 #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
532 GATE_IP_GSCL, 7, 0, 0),
557 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
563 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
583 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
619 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
633 GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
653 GATE_IP_ISP1, 7, 0, 0),
760 { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-pic32.c91 PINCTRL_PIN(7, "A7"),
407 PIC32_PINCTRL_FUNCTION(SDO3, RPA14R, 7),
433 PIC32_PINCTRL_FUNCTION(SDO3, RPA15R, 7),
458 PIC32_PINCTRL_FUNCTION(SS3OUT, RPB0R, 7),
484 PIC32_PINCTRL_FUNCTION(SDO3, RPB1R, 7),
491 PIC32_PINCTRL_FUNCTION(INT1, INT1R, 7),
492 PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 7),
493 PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 7),
494 PIC32_PINCTRL_FUNCTION(IC1, IC1R, 7),
495 PIC32_PINCTRL_FUNCTION(IC6, IC6R, 7),
[all …]
/linux/drivers/usb/isp1760/
H A Disp1760-core.c186 [HCC_ISOC_CACHE] = REG_FIELD(ISP176x_HC_HCCPARAMS, 7, 7),
188 [CMD_LRESET] = REG_FIELD(ISP176x_HC_USBCMD, 7, 7),
207 [PORT_SUSPEND] = REG_FIELD(ISP176x_HC_PORTSC1, 7, 7),
223 [HC_CHIP_ID_LOW] = REG_FIELD(ISP176x_HC_CHIP_ID, 0, 7),
233 [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 7, 7),
248 [HW_SW_SEL_HC_DC] = REG_FIELD(ISP176x_HC_OTG_CTRL, 7, 7),
259 [CMD_LRESET] = REG_FIELD(ISP1763_HC_USBCMD, 7, 7),
278 [PORT_SUSPEND] = REG_FIELD(ISP1763_HC_PORTSC1, 7, 7),
294 [HC_CHIP_REV] = REG_FIELD(ISP1763_HC_CHIP_REV, 0, 7),
303 [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 7, 7),
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Dqmi_wlfw_v01.h89 QMI_WLFW_CALIBRATION_V01 = 7,
269 #define WLFW_WLAN_MODE_RESP_MSG_V01_MAX_MSG_LEN 7
296 #define WLFW_WLAN_CFG_RESP_MSG_V01_MAX_MSG_LEN 7
349 #define WLFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7
366 #define WLFW_CAL_REPORT_RESP_MSG_V01_MAX_MSG_LEN 7
373 #define WLFW_INITIATE_CAL_DOWNLOAD_IND_MSG_V01_MAX_MSG_LEN 7
398 #define WLFW_CAL_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7
463 #define WLFW_MSA_READY_RESP_MSG_V01_MAX_MSG_LEN 7
478 #define WLFW_INI_RESP_MSG_V01_MAX_MSG_LEN 7
514 #define WLFW_ATHDIAG_WRITE_RESP_MSG_V01_MAX_MSG_LEN 7
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Dget-reg-list.c304 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[7]),
354 ARM64_SYS_REG(3, 1, 0, 0, 7), /* AIDR_EL1 */
359 ARM64_SYS_REG(2, 0, 0, 0, 7),
363 ARM64_SYS_REG(2, 0, 0, 1, 7),
369 ARM64_SYS_REG(2, 0, 0, 2, 7),
373 ARM64_SYS_REG(2, 0, 0, 3, 7),
377 ARM64_SYS_REG(2, 0, 0, 4, 7),
381 ARM64_SYS_REG(2, 0, 0, 5, 7),
385 ARM64_SYS_REG(2, 0, 0, 6, 7),
386 ARM64_SYS_REG(2, 0, 0, 7, 4),
[all …]
/linux/drivers/comedi/drivers/ni_routing/ni_route_values/
H A Dni_mseries.c64 [B(TRIGGER_LINE(7))] = I(25),
78 [B(NI_AO_StartTrigger)] = I(7),
96 [B(TRIGGER_LINE(7))] = I(25),
110 [B(NI_AO_StartTrigger)] = I(7),
128 [B(TRIGGER_LINE(7))] = I(25),
142 [B(NI_AO_StartTrigger)] = I(7),
160 [B(TRIGGER_LINE(7))] = I(25),
174 [B(NI_AO_StartTrigger)] = I(7),
192 [B(TRIGGER_LINE(7))] = I(25),
206 [B(NI_AO_StartTrigger)] = I(7),
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d2.dtsi284 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
286 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
293 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
303 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
315 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
353 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
359 AT91_XDMAC_DT_PERID(7))>;
435 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
449 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
466 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
[all …]
/linux/sound/soc/codecs/
H A Des8311.h16 #define ES8311_RESET_CSM_ON BIT(7)
22 #define ES8311_CLKMGR1_MCLK_SEL BIT(7)
30 #define ES8311_CLKMGR2_DIV_PRE_MASK GENMASK(7, 5)
38 #define ES8311_CLKMGR5_ADC_DIV_MASK GENMASK(7, 4)
52 #define ES8311_SDP_IN_SEL_SHIFT 7
73 #define ES8311_SYS3_PDN_ANA_SHIFT 7
111 #define ES8311_ADC4_ALC_EN_SHIFT 7
139 #define ES8311_DAC4_DRC_EN_SHIFT 7
152 #define ES8311_GPIO_ADC2DAC_SEL_SHIFT 7
/linux/drivers/net/ethernet/neterion/
H A Ds2io-regs.h63 #define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7)
74 #define ADAPTER_CNTL_EN s2BIT(7)
164 #define IIC_INT_REG_REQ_FSM_ERR s2BIT(7)
324 #define PFC_ECC_SG_ERR s2BIT(7)
359 #define TTI_ECC_SG_ERR s2BIT(7)
376 #define TPA_TX_FRM_DROP s2BIT(7)
427 #define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
436 #define TTI_CMD_MEM_WE s2BIT(7)
446 #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
447 #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
[all …]
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7,8,9",
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
57 "Counter": "0,1,2,3,4,5,6,7",
65 "Counter": "0,1,2,3,4,5,6,7,8,9",
91 "Counter": "0,1,2,3,4,5,6,7",
101 "Counter": "0,1,2,3,4,5,6,7,8,9",
128 "Counter": "0,1,2,3,4,5,6,7",
136 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
/linux/include/linux/power/
H A Dmax77705_charger.h20 #define MAX77705_AICL_I BIT(7)
30 #define MAX77705_AICL_IM BIT(7)
40 #define MAX77705_AICL_OK BIT(7)
84 #define MAX77705_PQEN_SHIFT 7
85 #define MAX77705_PQEN_MASK BIT(7)
91 #define MAX77705_OTG_ILIM_MASK GENMASK(7, 6)
103 #define MAX77705_SYS_TRACK_DIS_SHIFT 7
104 #define MAX77705_SYS_TRACK_DIS_MASK BIT(7)
112 #define MAX77705_CHG_MINVSYS_MASK GENMASK(7, 6)
151 #define MAX77705_CHG_EN_MASK BIT(7)
/linux/lib/crypto/arm/
H A Dchacha-neon-core.S30 * ChaCha has 16, 12, 8, and 7-bit rotations. For the 12 and 7-bit rotations,
90 // x2 += x3, x1 = rotl32(x1 ^ x2, 7)
93 vshl.u32 q1, q4, #7
120 // x2 += x3, x1 = rotl32(x1 ^ x2, 7)
123 vshl.u32 q1, q4, #7
205 .Lrol8_table: .byte 3, 0, 1, 2, 7, 4, 5, 6
329 // x8 += x12, x4 = rotl32(x4 ^ x8, 7)
330 // x9 += x13, x5 = rotl32(x5 ^ x9, 7)
331 // x10 += x14, x6 = rotl32(x6 ^ x10, 7)
332 // x11 += x15, x7 = rotl32(x7 ^ x11, 7)
[all …]
H A Dblake2s-core.S108 // b = ror32(b ^ c, 7);
127 // that they end up as (7, 8) after every round.
140 // (v[2], v[6], v[10], v[14]) and (v[3], v[7], v[11], v[15]).
148 .set brot, 7
161 // (v[2], v[7], v[8], v[13]) and (v[3], v[4], v[9], v[14]).
215 ldm r12, {r2-r7} // load IV[3..7]
219 eor r7, r7, r1 // v[15] = IV[7] ^ f[1]
223 // Load h[0..7] == v[0..7].
230 _blake2s_round 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
231 _blake2s_round 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-mt2701.h59 MTK_FUNCTION(7, "DBG_MON_A[0]")
61 MTK_PIN(PINCTRL_PIN(7, "SPI1_CSN"),
67 MTK_FUNCTION(7, "DBG_MON_B[12]")
76 MTK_FUNCTION(7, "DBG_MON_B[13]")
86 MTK_FUNCTION(7, "DBG_MON_B[14]")
119 MTK_FUNCTION(7, "DBG_MON_B[30]")
127 MTK_FUNCTION(7, "DBG_MON_B[31]")
154 MTK_FUNCTION(7, "DBG_MON_A[3]")
164 MTK_FUNCTION(7, "DBG_MON_A[5]")
176 MTK_FUNCTION(7, "DBG_MON_A[4]")
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-mickey.dts123 cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>,
124 <&cpu3 7 7>;
128 cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>,
129 <&cpu3 7 8>;
425 rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
431 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
435 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
/linux/drivers/platform/mellanox/
H A Dnvsw-sn2201.c87 #define NVSW_SN2201_MAIN_MUX_CH7_NR (NVSW_SN2201_MAIN_MUX_CH0_NR + 7)
631 .brdinfo = &nvsw_sn2201_static_devices[7],
679 .brdinfo = &nvsw_sn2201_static_devices[7],
705 .mask = GENMASK(7, 4),
710 .mask = GENMASK(7, 4),
715 .mask = GENMASK(7, 4),
720 .mask = GENMASK(7, 4),
725 .mask = GENMASK(7, 4),
730 .mask = GENMASK(7, 4),
735 .mask = GENMASK(7, 4),
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3528.c25 RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
39 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
58 RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
70 RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
81 RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
89 RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
119 RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
142 RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
149 RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
173 RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Draspberrypi,7inch-touchscreen-panel-regulator.yaml4 $id: http://devicetree.org/schemas/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml#
7 title: RaspberryPi 7" display ATTINY88-based regulator/backlight controller
13 The RaspberryPi 7" display has an ATTINY88-based regulator/backlight
15 and control the backlight. The V2 supports 5" and 7" panels and also
24 - raspberrypi,7inch-touchscreen-panel-regulator
42 compatible = "raspberrypi,7inch-touchscreen-panel-regulator";
/linux/include/linux/mfd/wcd934x/
H A Dregisters.h52 #define WCD934X_IRQ_EAR_PA_CNP_COMPLETE 7
82 #define WCD934X_ANA_BIAS_EN_MASK BIT(7)
83 #define WCD934X_ANA_BIAS_EN BIT(7)
89 #define WCD934X_ANA_RCO_BG_EN_MASK BIT(7)
90 #define WCD934X_ANA_RCO_BG_ENABLE BIT(7)
108 #define WCD934X_MBHC_L_DET_EN_MASK BIT(7)
109 #define WCD934X_MBHC_L_DET_EN BIT(7)
128 #define WCD934X_VTH_MASK GENMASK(7, 2)
136 #define WCD934X_MBHC_BTN_VTH_MASK GENMASK(7, 2)
139 #define WCD934X_ANA_MICB_EN_MASK GENMASK(7, 6)
[all …]
/linux/include/dt-bindings/clock/
H A Drk3399-ddr.h17 /* DDR3-1066 (7-7-7) */
21 /* DDR3-1333 (7-7-7) */
26 #define DDR3_1333H 7
/linux/lib/crypto/x86/
H A Dsha1-avx2-asm.S199 .if ((i & 7) == 0)
205 .elseif ((i & 7) == 1)
208 .elseif ((i & 7) == 2)
210 .elseif ((i & 7) == 4)
212 .elseif ((i & 7) == 7)
213 vmovdqu WY_TMP, PRECALC_WK(i&~7)
229 .if ((i & 7) == 0)
237 .elseif ((i & 7) == 1)
240 .elseif ((i & 7) == 2)
243 .elseif ((i & 7) == 3)
[all …]
/linux/include/linux/mfd/
H A Dtps65910.h169 #define PUADEN_EN3P_SHIFT 7
222 #define VDD1_OP_CMD_SHIFT 7
245 #define VDD2_OP_CMD_SHIFT 7
374 #define DEVCTRL_PWR_OFF_SHIFT 7
406 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
425 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
444 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
463 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
480 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
514 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
[all …]
/linux/drivers/media/i2c/
H A Dtda1997x_regs.h128 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
135 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
157 #define HPD_MAN_CTRL_HPD_PULSE BIT(7) /* HPD Pulse low 110ms */
163 #define RT_MAN_CTRL_RT_AUTO BIT(7)
175 #define VHREF_INT_DET BIT(7) /* interlace detect: 1=alt 0=frame */
207 #define FILTERS_CTRL_7TAP 2L /* 7 Taps */
208 #define FILTERS_CTRL_2_7TAP 3L /* 2/7 Taps */
212 #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
238 #define HDMI_FLAGS_AUDIO BIT(7) /* Audio packet in last videoframe */
273 #define CLK_CFG_INV_OUT_CLK BIT(7)
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-beagleboneai64.dts310 J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
311 J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
312 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
313 J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
314 J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
340 J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
346 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
352 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
364 J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
392 J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi68 avs_monitor: avs-monitor@7d5d2000 {
79 dma: dma-controller@7e007000 {
89 /* DMA lite 7 - 10 */
109 pm: watchdog@7e100000 {
125 rng@7e104000 {
130 uart2: serial@7e201400 {
141 uart3: serial@7e201600 {
152 uart4: serial@7e201800 {
163 uart5: serial@7e201a00 {
174 spi3: spi@7e204600 {
[all …]

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