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/qemu/target/s390x/tcg/
H A Dfpu_helper.c23 #include "s390x-internal.h"
25 #include "exec/helper-proto.h"
66 qemu_exc = env->fpu_status.float_exception_flags; in handle_exceptions()
70 env->fpu_status.float_exception_flags = 0; in handle_exceptions()
74 * IEEE-Underflow exception recognition exists if a tininess condition in handle_exceptions()
76 * - The mask bit in the FPC is zero and the result is inexact in handle_exceptions()
77 * - The mask bit in the FPC is one in handle_exceptions()
79 * underflow action in case the mask bit is not one. in handle_exceptions()
82 !((env->fpc >> 24) & S390_IEEE_MASK_UNDERFLOW)) { in handle_exceptions()
93 * triggering the trap - impossible right now. in handle_exceptions()
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/qemu/include/qemu/
H A Dbitops.h9 * See the COPYING.LIB file in the top-level directory.
16 #include "host-utils.h"
24 #define BIT(nr) (1UL << (nr)) macro
28 (((~0ULL) >> (64 - (length))) << (shift))
33 * We provide a set of functions which work on arbitrary-length arrays of
37 * - Bits stored in an array of 'unsigned long': set_bit(), clear_bit(), etc
38 * - Bits stored in an array of 'uint32_t': set_bit32(), clear_bit32(), etc
43 * be some guest-visible register view of the bit array.
56 * DOC: 'unsigned long' bit array APIs
63 * set_bit - Set a bit in memory
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H A Dhost-utils.h27 * version 2 or later. See the COPYING file in the top-level directory.
42 *phigh = r >> 64; in mulu64()
50 *phigh = r >> 64; in muls64()
53 /* compute with 96 bit intermediate result: (a*b)/c */
61 return ((__int128_t)a * b + c - 1) / c; in muldiv64_round_up()
67 __uint128_t dividend = ((__uint128_t)*phigh << 64) | *plow; in divu128()
71 *phigh = result >> 64; in divu128()
78 __int128_t dividend = ((__int128_t)*phigh << 64) | *plow; in divs128()
82 *phigh = result >> 64; in divs128()
109 rl += c - 1; in muldiv64_rounding()
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/qemu/docs/devel/
H A Dtcg-ops.rst1 .. _tcg-ops-ref:
43 a sequence of basic blocks connected by the fall-through paths of
60 .. code-block:: none
62 add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */
109 A 32-bit integer.
113 A 64-bit integer. For 32-bit hosts, such variables are split into a pair
116 host-endian representation.
131 A 128-bit integer. For all hosts, such variables are split into a number
134 host-endian representation.
138 A 64-bit vector. This type is valid only if the TCG target
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H A Dloads-stores.rst12 documentation of each API -- for that you should look at the
32 - (empty) : for 32 or 64 bit sizes
33 - ``u`` : unsigned
34 - ``s`` : signed
37 - ``b`` : 8 bits
38 - ``w`` : 16 bits
39 - ``24`` : 24 bits
40 - ``l`` : 32 bits
41 - ``q`` : 64 bits
44 - ``he`` : host endian
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/qemu/target/loongarch/tcg/
H A Dvec_helper.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2022-2023 Loongson Technology Corporation Limited
10 #include "exec/helper-proto.h"
15 #include "tcg/tcg-gvec-desc.h"
17 #define DO_ODD_EVEN(NAME, BIT, E1, E2, DO_OP) \ argument
24 typedef __typeof(Vd->E1(0)) TD; \
27 for (i = 0; i < oprsz / (BIT / 8); i++) { \
28 Vd->E1(i) = DO_OP((TD)Vj->E2(2 * i + 1), (TD)Vk->E2(2 * i)); \
34 DO_ODD_EVEN(vhaddw_d_w, 64, D, W, DO_ADD)
45 Vd->Q(i) = int128_add(int128_makes64(Vj->D(2 * i + 1)), in HELPER()
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/qemu/docs/system/arm/
H A Dvirt.rst1 .. _arm-virt:
10 idiosyncrasies and limitations of a particular bit of real-world
18 ``virt-5.0`` machine type will behave like the ``virt`` machine from
19 the QEMU 5.0 release, and migration should work between ``virt-5.0``
20 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
22 the non-versioned ``virt`` machine type.
24 VM migration is not guaranteed when using ``-cpu max``, as features
33 - PCI/PCIe devices
34 - Flash memory
35 - Either one or two PL011 UARTs for the NonSecure World
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/qemu/tests/qemu-iotests/
H A D28734 # This tests qocw2-specific low-level functionality
47 rm -f "$RAND_FILE"
55 output=$(_make_test_img -o 'compression_type=zstd' 64M; _cleanup_test_img)
56 if echo "$output" | grep -q "Parameter 'compression-type' does not accept value 'zstd'"; then
61 echo "=== Testing compression type incompatible bit setting for zlib ==="
63 _make_test_img -o compression_type=zlib 64M
64 _qcow2_dump_header --no-filter-compression | grep incompatible_features
67 echo "=== Testing compression type incompatible bit setting for zstd ==="
69 _make_test_img -o compression_type=zstd 64M
70 _qcow2_dump_header --no-filter-compression | grep incompatible_features
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/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_compile_64r6el.sh3 # Bit Count
4 # ---------
6 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_b.c \
7 -EL -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_b_64r6el
8 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_h.c \
9 -EL -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_h_64r6el
10 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_w.c \
11 -EL -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_w_64r6el
12 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_d.c \
13 -EL -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_d_64r6el
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H A Dtest_msa_compile_64r6eb.sh3 # Bit Count
4 # ---------
6 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_b.c \
7 -EB -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_b_64r6eb
8 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_h.c \
9 -EB -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_h_64r6eb
10 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_w.c \
11 -EB -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_w_64r6eb
12 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_d.c \
13 -EB -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_d_64r6eb
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/qemu/include/fpu/
H A Dsoftfloat-macros.h5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
9 * the SoftFloat-2a license
13 * taken to be licensed under the Softfloat-2a license unless specifically
19 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
25 National Science Foundation under grant MIP-9311980. The original version
26 of this code was written as part of a project to build a fixed-point vector
80 #include "fpu/softfloat-types.h"
81 #include "qemu/host-utils.h"
84 * shl_double: double-word merging left shift
85 * @l: left or most-significant word
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/qemu/configs/targets/
H A Driscv64-softmmu.mak4 …-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64b…
7 TARGET_LONG_BITS=64
H A Driscv64-linux-user.mak4 TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x…
7 TARGET_SYSTBL_ABI=64
8 TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret
10 TARGET_LONG_BITS=64
H A Driscv64-bsd-user.mak4 TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x…
5 TARGET_LONG_BITS=64
/qemu/target/i386/tcg/
H A Ddecode-new.h35 X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
52 X86_TYPE_I_unsigned, /* Immediate, zero-extended */
53 X86_TYPE_nop, /* modrm operand decoded but not loaded into s->T{0,1} */
54 X86_TYPE_2op, /* 2-operand RMW instruction */
55 X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
56 X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
64 X86_TYPE_ES, /* Hard-coded segment registers */
77 X86_SIZE_d, /* 32-bit */
78 X86_SIZE_dq, /* SSE/AVX 128-bit */
83 X86_SIZE_q, /* 64-bit */
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/qemu/hw/riscv/
H A Driscv-iommu-bits.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2023 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
10 * https://github.com/riscv-non-isa/riscv-iommu
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
23 * struct riscv_iommu_fq_record - Fault/Event Queue Record
40 * struct riscv_iommu_pq_record - PCIe Page Request record
66 #define RISCV_IOMMU_QUEUE_ENABLE BIT(0)
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/qemu/target/s390x/
H A Ds390x-internal.h7 * See the COPYING file in the top-level directory.
21 uint8_t pad1[0x80 - 0x18]; /* 0x018 */
37 uint8_t pad2[0xA8 - 0xA4]; /* 0x0a4 */
44 uint8_t pad3[0xc8 - 0xc4]; /* 0x0c4 */
46 uint8_t pad4[0xe8 - 0xcc]; /* 0x0cc */
48 uint8_t pad5[0xf4 - 0xf0]; /* 0x0f0 */
51 uint8_t pad6[0x110 - 0x100]; /* 0x100 */
53 uint8_t pad7[0x120 - 0x118]; /* 0x118 */
60 uint8_t pad8[0x1a0 - 0x180]; /* 0x180 */
67 uint8_t pad13[0x11b0 - 0x200]; /* 0x200 */
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H A Dcpu_features_def.h.inc5 * - _FEAT: Feature (enum) name used internally (S390_FEAT_##_FEAT)
6 * - _NAME: Feature name exposed to the user.
7 * - _TYPE: Feature type (S390_FEAT_TYPE_##_TYPE).
8 * - _BIT: Feature bit number within feature type block (unused for MISC).
9 * - _DESC: Feature description, exposed to the user.
18 * your option) any later version. See the COPYING file in the top-level
25 DEF_FEAT(DAT_ENH, "dateh", STFL, 3, "DAT-enhancement facility")
26 DEF_FEAT(IDTE_SEGMENT, "idtes", STFL, 4, "IDTE selective TLB segment-table clearing")
27 DEF_FEAT(IDTE_REGION, "idter", STFL, 5, "IDTE selective TLB region-table clearing")
28 DEF_FEAT(ASN_LX_REUSE, "asnlxr", STFL, 6, "ASN-and-LX reuse facility")
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/qemu/include/hw/timer/
H A Dmss-timer.h32 #define TYPE_MSS_TIMER "mss-timer"
36 * There are two 32-bit down counting timers.
37 * Timers 1 and 2 can be concatenated into a single 64-bit Timer
38 * that operates either in Periodic mode or in One-shot mode.
39 * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
40 * In 64-bit mode, writing to the 32-bit registers has no effect.
41 * Similarly, in 32-bit mode, writing to the 64-bit mode registers
42 * has no effect. Only two 32-bit timers are supported currently.
/qemu/include/
H A Delf.h4 /* 32-bit ELF base types. */
11 /* 64-bit ELF base types. */
47 #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
48 #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
49 #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
50 #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
51 #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
61 #define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */
81 #define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */
89 #define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra RM9000 */
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/qemu/tcg/tci/
H A DREADME1 TCG Interpreter (TCI) - Copyright (c) 2011 Stefan Weil.
24 tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci.
30 to six arguments packed into a 32-bit integer. See comments in tci.c
37 configure --enable-tcg-interpreter
39 If configure is called without --enable-tcg-interpreter, it will
46 configure --enable-tcg-interpreter
52 qemu-system-i386 -d in_asm,op_opt,cpu -D /tmp/qemu.log -accel tcg,one-insn-per-tb=on
61 configure --cpu=unknown --enable-tcg-interpreter
69 TCI needs special implementation for 32 and 64 bit host, 32 and 64 bit target,
73 | 32 64 32 64
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/qemu/linux-headers/asm-powerpc/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
100 * Contains EPCR, plus the upper half of 64-bit registers
101 * that are 32-bit on 32-bit implementations.
109 * IVORs are used -- contains IVOR0-15, plus additional IVORs
110 * in combination with an appropriate feature bit.
115 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
123 /* Enhanced debug -- DSRR0/1, SPRG9 */
126 /* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
131 * External Proxy (EXP) -- EPR
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/qemu/hw/misc/
H A Dallwinner-cpucfg.c26 #include "qemu/error-report.h"
29 #include "target/arm/arm-powerctl.h"
31 #include "hw/misc/allwinner-cpucfg.h"
55 REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
56 REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
57 REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
85 trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr); in allwinner_cpucfg_cpu_reset()
95 bool target_aa64 = arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64); in allwinner_cpucfg_cpu_reset()
97 ret = arm_set_cpu_on(cpu_id, s->entry_addr, 0, in allwinner_cpucfg_cpu_reset()
139 val = s->gen_ctrl; in allwinner_cpucfg_read()
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/qemu/util/
H A Dhost-utils.c27 #include "qemu/host-utils.h"
66 /* Unsigned 64x64 -> 128 multiplication */
72 /* Signed 64x64 -> 128 multiplication */
81 rh -= a; in muls64()
84 rh -= b; in muls64()
90 * Unsigned 128-by-64 division.
113 dhi = (dhi << sh) | (dlo >> (64 - sh)); in divu128()
123 dhighest = dhi >> (64 - sh); in divu128()
124 dhi = (dhi << sh) | (dlo >> (64 - sh)); in divu128()
132 * (dhi - divisor) < divisor in divu128()
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/qemu/target/avr/
H A Dtranslate.c4 * Copyright (c) 2019-2020 Michael Rolnik
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/qemu-print.h"
25 #include "exec/translation-block.h"
26 #include "tcg/tcg-op.h"
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
34 #include "exec/helper-info.c.inc"
42 * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
99 * A - instruction that can skip the next one
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