| #
85271269 |
| 10-Feb-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-tcg-20250208' of https://gitlab.com/rth7680/qemu into staging
meson: Disallow 64-bit on 32-bit emulation
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Merge tag 'pull-tcg-20250208' of https://gitlab.com/rth7680/qemu into staging
meson: Disallow 64-bit on 32-bit emulation
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# gpg: Signature made Sat 08 Feb 2025 15:46:23 EST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20250208' of https://gitlab.com/rth7680/qemu:
meson: Deprecate 32-bit host support
meson: Disallow 64-bit on 32-bit emulation
target/*: Remove TARGET_LONG_BITS from cpu-param.h
configure: Define TARGET_LONG_BITS in configs/targets/*.mak
gitlab-ci: Replace aarch64 with arm in cross-i686-tci build
meson: Disallow 64-bit on 32-bit HVF/NVMM/WHPX emulation
meson: Disallow 64-bit on 32-bit Xen emulation
meson: Disallow 64-bit on 32-bit KVM emulation
meson: Drop tcg as a module
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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|
| #
537600df |
| 31-Jan-2025 |
Richard Henderson <richard.henderson@linaro.org> |
configure: Define TARGET_LONG_BITS in configs/targets/*.mak
Define TARGET_LONG_BITS in each target's configure fragment.
Do this without removing the define in target/*/cpu-param.h
so that errors ar
configure: Define TARGET_LONG_BITS in configs/targets/*.mak
Define TARGET_LONG_BITS in each target's configure fragment.
Do this without removing the define in target/*/cpu-param.h
so that errors are caught like so:
In file included from .../src/include/exec/cpu-defs.h:26,
from ../src/target/hppa/cpu.h:24,
from ../src/linux-user/qemu.h:4,
from ../src/linux-user/hppa/cpu_loop.c:21:
../src/target/hppa/cpu-param.h:11: error: "TARGET_LONG_BITS" redefined [-Werror]
11 | #define TARGET_LONG_BITS 64
|
In file included from .../src/include/qemu/osdep.h:36,
from ../src/linux-user/hppa/cpu_loop.c:20:
./hppa-linux-user-config-target.h:32: note: this is the location of the previous definition
32 | #define TARGET_LONG_BITS 32
|
cc1: all warnings being treated as errors
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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|
| #
35ba77d2 |
| 02-Oct-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.2
* Add a property to set vl to ceil(AVL/2)
* Enable numamem testing for RISC-V
* Conside
Merge tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.2
* Add a property to set vl to ceil(AVL/2)
* Enable numamem testing for RISC-V
* Consider MISA bit choice in implied rule
* Fix the za64rs priv spec requirements
* Enable Bit Manip for OpenTitan Ibex CPU
* Fix the group bit setting of AIA with KVM
* Stop timer with infinite timecmp
* Add 'fcsr' register to QEMU log as a part of F extension
* Fix riscv64 build on musl libc
* Add preliminary textra trigger CSR functions
* RISC-V bsd-user support
* Respect firmware ELF entry point
* Add Svvptc extension support
* Fix masking of rv32 physical address
* Fix linking problem with semihosting disabled
* Fix IMSIC interrupt state updates
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# gpg: Signature made Wed 02 Oct 2024 06:47:02 BST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qemu: (35 commits)
bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
bsd-user: Implement 'get_mcontext' for RISC-V
bsd-user: Implement RISC-V signal trampoline setup functions
bsd-user: Define RISC-V signal handling structures and constants
bsd-user: Add generic RISC-V64 target definitions
bsd-user: Define RISC-V system call structures and constants
bsd-user: Define RISC-V VM parameters and helper functions
bsd-user: Add RISC-V thread setup and initialization support
bsd-user: Implement RISC-V sysarch system call emulation
bsd-user: Add RISC-V signal trampoline setup function
bsd-user: Define RISC-V register structures and register copying
bsd-user: Add RISC-V ELF definitions and hardware capability detection
bsd-user: Implement RISC-V TLS register setup
bsd-user: Implement RISC-V CPU register cloning and reset functions
bsd-user: Add RISC-V CPU execution loop and syscall handling
bsd-user: Implement RISC-V CPU initialization and main loop
hw/intc: riscv-imsic: Fix interrupt state updates.
target/riscv/cpu_helper: Fix linking problem with semihosting disabled
target/riscv32: Fix masking of physical address
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| #
74b49324 |
| 16-Sep-2024 |
Warner Losh <imp@bsdimp.com> |
bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Aje
bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-18-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|