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/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc86 XTREG( 62,248,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
123 …62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:…
125 …62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:…
127 …62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:…
129 …62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:…
131 …62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62…
133 …62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62…
135 …62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62…
137 …62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62…
139 …62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62…
[all …]
/qemu/tests/qtest/
H A Dpnv-xive2-common.h43 #define XIVE_IC_BAR ((0x3ull << 62) | XIVE_IC_ADDR)
46 #define XIVE_ESB_BAR ((0x3ull << 62) | XIVE_ESB_ADDR)
49 #define XIVE_NVPG_BAR ((0x3ull << 62) | XIVE_NVPG_ADDR)
51 #define XIVE_NVC_BAR ((0x3ull << 62) | XIVE_NVC_ADDR)
/qemu/target/ppc/
H A Dcpu-param.h13 * Note that the official physical address space bits is 62-M where M
17 #define TARGET_PHYS_ADDR_SPACE_BITS 62
H A Dcpu.c116 priv = ciabr & PPC_BITMASK(62, 63); in ppc_update_ciabr()
145 bool sv = extract32(dawrx, PPC_BIT_NR(62), 1); in ppc_update_daw()
146 bool pr = extract32(dawrx, PPC_BIT_NR(62), 1); in ppc_update_daw()
H A Dmmu-hash64.h35 #define SLB_VSID_SSIZE_SHIFT 62
75 #define HPTE64_V_SSIZE_SHIFT 62
/qemu/tests/tcg/s390x/
H A Drxsbg.c25 rxsbg(&r1, 3, 61 | 0x80, 62, 1, &cc); in test_cc0()
35 rxsbg(&r1, 3, 61 | 0x80, 62, 1, &cc); in test_cc1()
/qemu/target/alpha/
H A Dgdbstub.c34 case 32 ... 62: in alpha_cpu_gdb_read_register()
69 case 32 ... 62: in alpha_cpu_gdb_write_register()
/qemu/tests/qemu-iotests/
H A D03674 $PYTHON qcow2.py "$TEST_IMG" set-feature-bit incompatible 62
90 # With feature table containing bits 61 and 62
H A D076.out28 62 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
/qemu/target/hexagon/
H A Darch.c50 {62, 76, 90, 104},
54 {51, 62, 73, 85},
60 {37, 45, 54, 62},
107 61, 62, 62, 63
H A Dhex_regs.h80 HEX_REG_UTIMERLO = 62,
H A Dfma_emu.c146 a.round = (int128_getlo(a.mant) >> 62) & 1; in accum_norm_right()
189 if (int128_gethi(a.mant) & (1ULL << 62)) { in accum_sub()
242 if (int128_gethi(a.mant) & (1ULL << 62)) { in accum_add()
/qemu/hw/microblaze/
H A Dpetalogix_s3adsp1800_mmu.c128 /* 2 timers at irq 2 @ 62 Mhz. */ in OBJECT_DECLARE_TYPE()
132 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); in OBJECT_DECLARE_TYPE()
/qemu/target/loongarch/
H A Dcpu-csr.h76 FIELD(TLBENTRY_64, NX, 62, 1)
166 FIELD(CSR_TLBRERA, PC, 2, 62)
/qemu/target/hppa/
H A Dgdbstub.c129 case 62: in hppa_cpu_gdb_read_register()
259 case 62: in hppa_cpu_gdb_write_register()
/qemu/hw/intc/
H A Dspapr_xive.c917 * Bit 62: the full function page supports trigger
929 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
1019 * Bit 62: set the "eisn" in the EAS
1042 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
1302 * Bits 0-62: Reserved
1466 * Bits 0-62: Reserved
1476 * Bit 62: The value of Event Queue Generation Number (g) per
1560 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; in h_int_get_queue_config()
1662 * Bits 0-62: Reserved
H A Dgicv3_internal.h151 FIELD(GICR_PENDBASER, PTZ, 62, 1)
168 FIELD(GICR_VPENDBASER, IDAI, 62, 1)
198 #define ICC_RPR_EL1_NSNMI (1ULL << 62)
252 #define ICH_LR_EL2_STATE_SHIFT 62
296 FIELD(GITS_BASER, INDIRECT, 62, 1)
/qemu/hw/net/rocker/
H A Drocker_fp.h23 #define ROCKER_FP_PORTS_MAX 62
/qemu/linux-user/loongarch64/
H A Dsyscall.tbl80 62 32 llseek sys_llseek
81 62 64 lseek sys_lseek
/qemu/linux-user/hexagon/
H A Dsyscall.tbl80 62 32 llseek sys_llseek
81 62 64 lseek sys_lseek
/qemu/linux-user/riscv/
H A Dsyscall.tbl80 62 32 llseek sys_llseek
81 62 64 lseek sys_lseek
/qemu/linux-user/openrisc/
H A Dsyscall.tbl80 62 32 llseek sys_llseek
81 62 64 lseek sys_lseek
/qemu/linux-user/aarch64/
H A Dsyscall_64.tbl80 62 32 llseek sys_llseek
81 62 64 lseek sys_lseek
/qemu/target/riscv/
H A Dcpu_bits.h364 #define SMSTATEEN0_HSENVCFG (1ULL << 62)
804 #define MENVCFG_PBMTE (1ULL << 62)
1034 #define MCYCLECFG_BIT_MINH BIT_ULL(62)
1045 #define MINSTRETCFG_BIT_MINH BIT_ULL(62)
1058 #define MHPMEVENT_BIT_MINH BIT_ULL(62)
/qemu/hw/ppc/
H A Dvirtex_ml507.c232 /* 2 timers at irq 2 @ 62 Mhz. */ in virtex_init()
236 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); in virtex_init()

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