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/qemu/tests/tcg/alpha/system/
H A Dboot.S198 * the result is in $27. Register $28 may be clobbered; everything else
201 * We store the remainder in $28, so that we can share code.
228 #define modulus $28
272 * Note that __divqu above leaves the result in $28.
286 mov $28, $27
301 bis $24, $25, $28
302 bge $28, __divqu
311 subq $31, $24, $28
312 cmovlt $24, $28, $24
313 subq $31, $25, $28
[all …]
/qemu/tests/qemu-iotests/
H A D026.out30 Event: l1_update; errno: 28; imm: off; once: on; write
35 Event: l1_update; errno: 28; imm: off; once: on; write -b
40 Event: l1_update; errno: 28; imm: off; once: off; write
47 Event: l1_update; errno: 28; imm: off; once: off; write -b
86 Event: l2_load; errno: 28; imm: off; once: on; write
94 Event: l2_load; errno: 28; imm: off; once: on; write -b
102 Event: l2_load; errno: 28; imm: off; once: off; write
110 Event: l2_load; errno: 28; imm: off; once: off; write -b
142 Event: l2_update; errno: 28; imm: off; once: on; write
147 Event: l2_update; errno: 28; imm: off; once: on; write -b
[all …]
H A D026.out.nocache30 Event: l1_update; errno: 28; imm: off; once: on; write
35 Event: l1_update; errno: 28; imm: off; once: on; write -b
40 Event: l1_update; errno: 28; imm: off; once: off; write
47 Event: l1_update; errno: 28; imm: off; once: off; write -b
86 Event: l2_load; errno: 28; imm: off; once: on; write
94 Event: l2_load; errno: 28; imm: off; once: on; write -b
102 Event: l2_load; errno: 28; imm: off; once: off; write
110 Event: l2_load; errno: 28; imm: off; once: off; write -b
146 Event: l2_update; errno: 28; imm: off; once: on; write
152 Event: l2_update; errno: 28; imm: off; once: on; write -b
[all …]
H A D197.out45 28 KiB (0x7000) bytes not allocated at offset 0 bytes (0x0)
46 2 KiB (0x800) bytes allocated at offset 28 KiB (0x7000)
49 28 KiB (0x7000) bytes not allocated at offset 36 KiB (0x9000)
52 28 KiB (0x7000) bytes not allocated at offset 0 bytes (0x0)
53 8 KiB (0x2000) bytes allocated at offset 28 KiB (0x7000)
54 28 KiB (0x7000) bytes not allocated at offset 36 KiB (0x9000)
/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc23 F2(RRE, R(1,24), R(2,28))
24 F3(RRD, R(1,16), R(2,28), R(3,24))
25 F4(RRF_a, R(1,24), R(2,28), R(3,16), M(4,20))
26 F4(RRF_b, R(1,24), R(2,28), R(3,16), M(4,20))
27 F4(RRF_c, R(1,24), R(2,28), M(3,16), M(4,20))
28 F4(RRF_d, R(1,24), R(2,28), M(3,16), M(4,20))
29 F4(RRF_e, R(1,24), R(2,28), M(3,16), M(4,20))
61 F5(VRI_e, V(1,8), V(2,12), I(3,16,12), M(5,28), M(4,32))
62 F5(VRI_f, V(1,8), V(2,12), V(3,16), M(5,24), I(4,28,8))
63 F5(VRI_g, V(1,8), V(2,12), I(4,16,8), M(5,24), I(3,28,8))
[all …]
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dxtensa-modules.c.inc226 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
234 tie_t = (val << 28) >> 28;
242 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
250 tie_t = (val << 28) >> 28;
258 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
266 tie_t = (val << 28) >> 28;
274 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
282 tie_t = (val << 28) >> 28;
290 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
298 tie_t = (val << 28) >> 28;
[all …]
/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc116 { "LLR_BUF_3", 28, 1 },
380 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
388 tie_t = (val << 28) >> 28;
396 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
404 tie_t = (val << 28) >> 28;
412 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
420 tie_t = (val << 28) >> 28;
428 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
436 tie_t = (val << 28) >> 28;
444 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
[all …]
/qemu/target/xtensa/core-lx106/
H A Dxtensa-modules.c.inc155 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
163 tie_t = (val << 28) >> 28;
171 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
179 tie_t = (val << 28) >> 28;
187 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
195 tie_t = (val << 28) >> 28;
203 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
211 tie_t = (val << 28) >> 28;
219 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
227 tie_t = (val << 28) >> 28;
[all …]
/qemu/tests/tcg/s390x/
H A Dchrl.c21 cc = program_mask >> 28; in test_chrl()
36 cc = program_mask >> 28; in test_chrl()
56 cc = program_mask >> 28; in test_cghrl()
71 cc = program_mask >> 28; in test_cghrl()
/qemu/hw/intc/
H A Dpnv_xive2_regs.h68 #define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28)
120 #define CQ_TAR_ENTRY_SELECT PPC_BITMASK(28, 31)
186 #define VC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31)
197 #define VC_AT_MACRO_KILL_BLOCK_ID PPC_BITMASK(28, 31)
231 #define VC_ESBC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */
233 #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */
253 #define VC_EASC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */
255 #define VC_EASC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */
312 #define VC_ENDC_WATCH_BLOCK_ID PPC_BITMASK(28, 31)
371 #define PC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31)
[all …]
/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc181 #define STATE_PSCALLINC 28
219 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
227 tie_t = (val << 28) >> 28;
235 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
243 tie_t = (val << 28) >> 28;
251 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
259 tie_t = (val << 28) >> 28;
267 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
275 tie_t = (val << 28) >> 28;
283 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
[all …]
/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc229 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
237 tie_t = (val << 28) >> 28;
245 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
253 tie_t = (val << 28) >> 28;
261 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
269 tie_t = (val << 28) >> 28;
277 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
285 tie_t = (val << 28) >> 28;
293 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
301 tie_t = (val << 28) >> 28;
[all …]
/qemu/target/mips/
H A Dcpu.h55 #define FCR0_UFRP 28
113 #define CP0MVPC0_GS 28
233 * Register 28 Register 29 Register 30 Register 31
274 #define CP0_REGISTER_28 28
431 /* CP0 Register 28 */
480 #define CP0TCSt_TCU0 28
696 #define CP0PC_XK 28
768 #define CP0St_CU0 28
797 #define CP0SRSMap_SSV7 28
811 #define CP0Ca_CE 28
[all …]
/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc311 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
319 tie_t = (val << 28) >> 28;
327 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
335 tie_t = (val << 28) >> 28;
343 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
351 tie_t = (val << 28) >> 28;
359 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
367 tie_t = (val << 28) >> 28;
375 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
383 tie_t = (val << 28) >> 28;
[all …]
/qemu/include/hw/s390x/
H A Ds390-pci-inst.h27 #define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED 28
42 #define ZPCI_MOD_ST_DMAAS_INVAL 28
58 #define ZPCI_STPCIFC_ST_INVAL_DMAAS 28
87 #define FIB_DATA_ISC(x) (((x) >> 28) & 0x7)
/qemu/pc-bios/s390-ccw/
H A Dcio.h385 " srl %0,28\n" in stsch_err()
401 " srl %0,28" in msch()
416 " srl %0,28\n" in msch_err()
432 " srl %0,28" in tsch()
447 " srl %0,28\n" in ssch()
463 " srl %0,28" in csch()
477 " srl %0,28" in tpi()
492 " srl %0,28\n" in chsc()
/qemu/hw/ide/
H A Dahci-internal.h107 AHCI_PORT_REG_VENDOR_1 = 28, /* PxVS: Vendor Specific */
131 AHCI_PORT_IRQ_BIT_HBDS = 28,
143 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
179 #define PORT_CMD_ICC_MASK (0xfU << 28) /* i/f ICC state mask */
180 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
181 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
182 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
191 #define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */
H A Dide-internal.h72 #define WIN_READ 0x20 /* 28-Bit */
73 #define WIN_READ_ONCE 0x21 /* 28-Bit w/o retries, obsolete since ATA5 */
85 #define WIN_WRITE 0x30 /* 28-Bit */
86 #define WIN_WRITE_ONCE 0x31 /* 28-Bit w/o retries, obsolete since ATA5 */
97 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit, obsolete since ATA4 */
101 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
102 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - w/o retries, obsolete since ATA5 */
159 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - w/o retries, obsolete since ATA5 */
161 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - w/o retries, obsolete since ATA5 */
/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc248 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
256 tie_t = (val << 28) >> 28;
264 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
272 tie_t = (val << 28) >> 28;
280 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
288 tie_t = (val << 28) >> 28;
296 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
304 tie_t = (val << 28) >> 28;
312 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
320 tie_t = (val << 28) >> 28;
[all …]
/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc283 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
291 tie_t = (val << 28) >> 28;
299 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
307 tie_t = (val << 28) >> 28;
315 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
323 tie_t = (val << 28) >> 28;
331 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
339 tie_t = (val << 28) >> 28;
347 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
355 tie_t = (val << 28) >> 28;
[all …]
/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc217 #define STATE_EXCCAUSE 28
270 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
278 tie_t = (val << 28) >> 28;
286 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
294 tie_t = (val << 28) >> 28;
302 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
310 tie_t = (val << 28) >> 28;
335 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
343 tie_t = (val << 28) >> 28;
385 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
[all …]
/qemu/include/hw/misc/
H A Daspeed_scu.h102 * 30:28 Video Engine clock slow down setting
162 * 28:27 DRAM size setting (for VGA driver use)
268 * 28 Reserved (1)
299 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28)
339 * 28:26 H-PLL Parameters
362 * 30:28 I3C clock divider selection
384 * 28 Reserved
/qemu/linux-user/ppc/
H A Dvdso.S119 .cfi_offset 28, 28 * sizeof_reg
155 .cfi_offset 60, offsetof_mcontext_fregs + 28 * sizeof_freg
214 save_vreg 28
/qemu/linux-user/hppa/
H A Dvdso.S84 .cfi_offset 28, offsetof_sigcontext_gr + 28 * 4
138 .cfi_offset 80, offsetof_sigcontext_fr + 28 * 8
139 .cfi_offset 81, offsetof_sigcontext_fr + 28 * 8 + 4
/qemu/target/ppc/translate/
H A Dvmx-ops.c.inc45 GEN_VXFORM_300(vextubrx, 6, 28),
49 GEN_VXFORM_300(vsrv, 2, 28),
62 GEN_VXFORM_300(bcdtrunc, 0, 28),
82 GEN_VXFORM(vsum4sbs, 4, 28),
157 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),

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