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/qemu/hw/mips/
H A Dbootloader.c44 BL_REG_K0 = 26,
90 insn = deposit32(insn, 26, 6, opcode); in bl_gen_r_type()
109 insn = deposit32(insn, 26, 6, opcode); in bl_gen_i_type()
135 insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */ in bl_gen_jalr()
150 insn = deposit32(insn, 26, 6, 0b111000); in bl_gen_lui_nm()
170 insn = deposit32(insn, 26, 6, 0b100000); in bl_gen_ori_nm()
188 insn = deposit32(insn, 26, 6, 0b100001); in bl_gen_sw_nm()
/qemu/tests/functional/
H A Dtest_loongarch64_virt.py21 'releases/download/2024-11-26/vmlinuz.efi'),
25 'releases/download/2024-11-26/ramdisk'),
29 'releases/download/2024-11-26/QEMU_EFI.fd'),
/qemu/include/hw/misc/
H A Dlasi.h47 | LASI_BIT(26))
60 #define LASI_IRQ_PS2KBD_HPA 26
61 #define LASI_IRQ_PS2MOU_HPA 26
H A Daspeed_scu.h104 * 26 2D Engine GCLK clock throttling enable
163 * 26:24 DRAM configuration setting
270 * 26 Enable eSPI flash mode
302 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26)
339 * 28:26 H-PLL Parameters
363 * 26:24 MAC AHB clock divider selection
H A Dimx_ccm.h20 #define PD(v) (((v) >> 26) & 0xf)
25 #define PLL_PD(x) (((x) & 0xf) << 26)
H A Dimx31_ccm.h43 #define IMX31_CCM_MAX_REG 26
49 #define CCMR_FPMF (1<<26)
H A Dxlnx-versal-crl.h59 FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
70 FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
80 FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
86 FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
/qemu/tcg/mips/
H A Dtcg-target.c.inc221 OPC_J = 002 << 26,
222 OPC_JAL = 003 << 26,
223 OPC_BEQ = 004 << 26,
224 OPC_BNE = 005 << 26,
225 OPC_BLEZ = 006 << 26,
226 OPC_BGTZ = 007 << 26,
227 OPC_ADDIU = 011 << 26,
228 OPC_SLTI = 012 << 26,
229 OPC_SLTIU = 013 << 26,
230 OPC_ANDI = 014 << 26,
[all …]
/qemu/hw/intc/
H A Dxlnx-zynqmp-ipi.c52 FIELD(IPI_TRIG, PL_2, 26, 1)
64 FIELD(IPI_OBS, PL_2, 26, 1)
76 FIELD(IPI_ISR, PL_2, 26, 1)
88 FIELD(IPI_IMR, PL_2, 26, 1)
100 FIELD(IPI_IER, PL_2, 26, 1)
112 FIELD(IPI_IDR, PL_2, 26, 1)
135 int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27};
/qemu/include/hw/usb/
H A Ddwc2-regs.h97 #define GUSBCFG_ICUSBCAP BIT(26)
145 #define GINTSTS_PTXFEMP BIT(26)
219 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
220 #define GI2CCTL_I2CDEVADDR_SHIFT 26
242 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
243 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
304 #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
305 #define GHWCFG4_NUM_IN_EPS_SHIFT 26
395 #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
556 #define DXEPCTL_CNAK BIT(26)
[all …]
/qemu/include/libdecnumber/
H A DdecNumberLocal.h179 18,19,20,21,22,23,24,25,26,27,28,29,30,31,32, \
436 #define GETEXP(df) ((Int)(DECCOMBEXP[DFWORD((df), 0)>>26]+GETECON(df)))
440 #define GETMSD(df) (DECCOMBMSD[DFWORD((df), 0)>>26])
481 *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
487 *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
498 *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
509 *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
511 dpd2bcd8(bcd+4, ((sourhi)<<6) | (sourmh>>26)); \
528 *(bcd)=(uByte)DECCOMBMSD[sourhi>>26]; \
530 dpd2bcd8(bcd+4, ((sourhi)<<6) | (sourmh>>26)); \
[all …]
/qemu/linux-user/ppc/
H A Dvdso.S117 .cfi_offset 26, 26 * sizeof_reg
153 .cfi_offset 58, offsetof_mcontext_fregs + 26 * sizeof_freg
212 save_vreg 26
/qemu/linux-user/hppa/
H A Dvdso.S82 .cfi_offset 26, offsetof_sigcontext_gr + 26 * 4
134 .cfi_offset 76, offsetof_sigcontext_fr + 26 * 8
135 .cfi_offset 77, offsetof_sigcontext_fr + 26 * 8 + 4
/qemu/linux-user/loongarch64/
H A Dvdso.S83 .cfi_offset 26, B_GR + 26 * 8
117 .cfi_offset 58, B_FR + 26 * 8
/qemu/linux-headers/asm-generic/
H A Dhugetlb_encode.h9 * bits [26:31] of the flag arguments. The value in these 6 bits
20 #define HUGETLB_FLAG_ENCODE_SHIFT 26
/qemu/tests/tcg/alpha/system/
H A Dboot.S101 bsr $26, main !samegp
109 .frame $sp, 0, $26, 0
129 bsr $26, __sys_outs !samegp
130 bsr $26, _exit !samegp
146 .frame $sp, 0, $26, 0
168 .frame $sp, 0, $26, 0
/qemu/include/hw/acpi/
H A Dtpm.h51 #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */
52 #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */
53 #define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */
239 * TPM_STS mask for read bits 31:26 must be zero
/qemu/target/mips/
H A Dcpu.h220 * Register 24 Register 25 Register 26 Register 27
272 #define CP0_REGISTER_26 26
427 /* CP0 Register 26 */
698 #define CP0PC_XU 26
770 #define CP0St_FR 26
788 #define CP0IntCtl_IPPCI 26
791 #define CP0SRSCtl_HSS 26
813 #define CP0Ca_PCI 26
889 #define CP0C3_BI 26
1021 #define CP0DB_Halt 26
[all …]
/qemu/linux-user/riscv/
H A Dvdso.S141 .cfi_offset 26, B_GR + 26 * sizeof_reg
174 .cfi_offset 58, B_FR + 26 * sizeof_freg
/qemu/tests/tcg/tricore/asm/
H A Dtest_dextr.S32 TEST_D_DDI(dextr, 26, 0x02468acf, 0xabcdef01, 0x23456789, 25)
33 TEST_D_DDI(dextr, 27, 0x048d159e, 0xabcdef01, 0x23456789, 26)
68 TEST_D_DDD(dextr, 60, 0x048d159e, 0xabcdef01, 0x23456789, 26)
/qemu/tests/tcg/arm/
H A Dfcvt.ref56 26 SINGLE: 1.11100003258488635273e+30 / 0x71605d5b (0 => OK)
57 26 HALF: 0x7c00 (0x14 => OVERFLOW INEXACT )
119 26 SINGLE: 1.11100003258488635273e+30 / 0x71605d5b (0 => OK)
120 26 DOUBLE: 1.11100003258488635273e+30 / 0x00462c0bab60000000 (0 => OK)
182 26 DOUBLE: 3.14159265358979311600e+00 / 0x00400921fb54442d18 (0 => OK)
183 26 HALF: 0x03 (0x10 => INEXACT )
265 26 DOUBLE: 3.14159265358979311600e+00 / 0x00400921fb54442d18 (0 => OK)
266 26 SINGLE: 3.14159274101257324219e+00 / 0x40490fdb (0x10 => INEXACT )
419 26 SINGLE: 1.11100003258488635273e+30 / 0x71605d5b (0 => OK)
420 26 HALF: 0x7c00 (0x14 => OVERFLOW INEXACT )
[all …]
/qemu/tests/tcg/aarch64/
H A Dfcvt.ref56 26 SINGLE: 1.11100003258488635273e+30 / 0x71605d5b (0 => OK)
57 26 HALF: 0x7c00 (0x14 => OVERFLOW INEXACT )
119 26 SINGLE: 1.11100003258488635273e+30 / 0x71605d5b (0 => OK)
120 26 DOUBLE: 1.11100003258488635273e+30 / 0x00462c0bab60000000 (0 => OK)
182 26 DOUBLE: 3.14159265358979311600e+00 / 0x00400921fb54442d18 (0 => OK)
183 26 HALF: 0x4248 (0x10 => INEXACT )
265 26 DOUBLE: 3.14159265358979311600e+00 / 0x00400921fb54442d18 (0 => OK)
266 26 SINGLE: 3.14159274101257324219e+00 / 0x40490fdb (0x10 => INEXACT )
419 26 SINGLE: 1.11100003258488635273e+30 / 0x71605d5b (0 => OK)
420 26 HALF: 0x7c00 (0x14 => OVERFLOW INEXACT )
[all …]
/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc114 { "LLR_BUF_1", 26, 1 },
476 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1207 tie_t = (val << 26) >> 27;
1740 tie_t = (val << 26) >> 28;
1759 tie_t = (val << 26) >> 28;
1778 tie_t = (val << 26) >> 28;
2218 tie_t = (val << 26) >> 28;
2338 tie_t = (val << 26) >> 28;
2348 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2380 tie_t = (val << 26) >> 31;
[all …]
/qemu/target/hexagon/
H A Darch.c67 {26, 31, 37, 43},
71 {21, 26, 30, 35},
74 {18, 22, 26, 30},
103 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
115 23, 24, 24, 25, 26, 26, 27, 27, 28, 29,
/qemu/target/mips/tcg/
H A Dtranslate.c55 OPC_SPECIAL = (0x00 << 26),
56 OPC_REGIMM = (0x01 << 26),
57 OPC_CP0 = (0x10 << 26),
58 OPC_CP2 = (0x12 << 26),
59 OPC_CP3 = (0x13 << 26),
60 OPC_SPECIAL2 = (0x1C << 26),
61 OPC_SPECIAL3 = (0x1F << 26),
63 OPC_ADDI = (0x08 << 26),
64 OPC_ADDIU = (0x09 << 26),
65 OPC_SLTI = (0x0A << 26),
[all …]

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