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/qemu/target/openrisc/
H A Ddisas.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * You should have received a copy of the GNU General Public License
43 return -1; in print_insn_or1k()
54 static bool trans_l_##opcode(disassemble_info *info, arg_l_##opcode *a) \
60 INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b)
61 INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b)
62 INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b)
63 INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b)
64 INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b)
65 INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b)
[all …]
/qemu/tests/tcg/i386/
H A Dtest-i386-fp-exceptions.c17 volatile union u ld_invalid_1 = { .s = { 1, 1234 } };
32 #define IE (1 << 0)
33 #define ZE (1 << 2)
34 #define OE (1 << 3)
35 #define UE (1 << 4)
36 #define PE (1 << 5)
50 __asm__ volatile ("fnstsw" : "=a" (sw)); in main()
53 ret = 1; in main()
57 __asm__ volatile ("fnstsw" : "=a" (sw)); in main()
60 ret = 1; in main()
[all …]
H A Dtest-i386-fxam.c11 volatile union u ld_pseudo_m16382 = { .s = { UINT64_C(1) << 63, 0 } };
12 volatile union u ld_pseudo_nm16382 = { .s = { UINT64_C(1) << 63, 0x8000 } };
13 volatile union u ld_invalid_1 = { .s = { 1, 1234 } };
16 volatile union u ld_invalid_4 = { .s = { (UINT64_C(1) << 63) - 1, 0x7fff } };
17 volatile union u ld_invalid_n1 = { .s = { 1, 0x8123 } };
20 volatile union u ld_invalid_n4 = { .s = { (UINT64_C(1) << 63) - 1, 0xffff } };
22 #define C0 (1 << 8)
23 #define C1 (1 << 9)
24 #define C2 (1 << 10)
25 #define C3 (1 << 14)
[all …]
H A Dtest-i386.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * You should have received a copy of the GNU General Public License
37 #define TEST_CMOV 1
38 #define TEST_FCOMI 1
189 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
197 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
205 : "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
352 asm("movl $1, %0\n\t"\
353 "cmpl %2, %1\n\t"\
354 "j" JCC " 1f\n\t"\
[all …]
H A Dtest-i386-fprem.c19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * You should have received a copy of the GNU General Public License
41 unsigned int one:1;
43 unsigned int negative:1;
50 unsigned int quiet_nan:1;
51 unsigned int one:1;
53 unsigned int negative:1;
63 .ieee_nan.one = 1,
64 .ieee_nan.quiet_nan = 1,
71 .ieee_nan.one = 1,
[all …]
/qemu/target/hexagon/
H A Dfma_emu.c11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * You should have received a copy of the GNU General Public License
50 return mant | 1ULL << 52; in float64_getmant()
68 return exp + 1; in float64_getexp()
70 return -1; in float64_getexp()
80 return exp + 1; in float32_getexp()
82 return -1; in float32_getexp()
93 static Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow) in int128_sub_borrow() argument
95 Int128 ret = int128_sub(a, b); in int128_sub_borrow()
121 static Accum accum_norm_left(Accum a) in accum_norm_left() argument
[all …]
H A Dmacros.h11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * You should have received a copy of the GNU General Public License
62 * Slot 1 store with slot 0 load
63 * A slot 1 store operation with a slot 0 load operation can appear in a packet.
67 * memw(R5) = R2 // slot 1 store
71 * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
78 * For qemu, we look for a load in slot 0 when there is a store in slot 1
79 * in the same packet. When we see this, we call a helper that probes the
88 process_store(ctx, 1); \
102 process_store(ctx, 1); \
[all …]
/qemu/target/loongarch/
H A Dvec.h15 #define D(x) D[(x) ^ 1]
19 #define UD(x) UD[(x) ^ 1]
33 #define DO_ADD(a, b) (a + b) argument
34 #define DO_SUB(a, b) (a - b) argument
35 #define DO_VAVG(a, b) ((a >> 1) + (b >> 1) + (a & b & 1)) argument
36 #define DO_VAVGR(a, b) ((a >> 1) + (b >> 1) + ((a | b) & 1)) argument
37 #define DO_VABSD(a, b) ((a > b) ? (a -b) : (b-a)) argument
38 #define DO_VABS(a) ((a < 0) ? (-a) : (a)) argument
39 #define DO_MIN(a, b) (a < b ? a : b) argument
40 #define DO_MAX(a, b) (a > b ? a : b) argument
[all …]
/qemu/tests/tcg/openrisc/
H A Dtest_lf_lts.c5 int a; in main() local
9 a = 0; in main()
12 result = 1; in main()
16 "lf.sflt.s %1, %2\n\t" in main()
19 : "+r"(a) in main()
22 if (a != result) { in main()
24 return -1; in main()
27 a = 0; in main()
33 ("1:\n\t" in main()
34 "lf.add.s %1, %1, %3\n\t" in main()
[all …]
H A Dtest_lx.c5 int a; in main() local
12 "l.sb 0x4 + %1, r8\n\t" in main()
14 "l.lbz %0, 0x4 + %1\n\t" in main()
15 : "=r"(a), "+m"(*p) in main()
17 if (a != result) { in main()
18 printf("lbz error, %x\n", a); in main()
19 return -1; in main()
24 ("l.lbs %0, 0x4 + %1\n\t" in main()
25 : "=r"(a) in main()
28 if (a != result) { in main()
[all …]
H A Dtest_logic.c5 int a, b, c; in main() local
12 ("l.sll %0, %1, %2\n\t" in main()
13 : "=r"(a) in main()
16 if (a != result) { in main()
18 return -1; in main()
24 ("l.slli %0, %1, 0x2\n\t" in main()
25 : "=r"(a) in main()
28 if (a != result) { in main()
30 return -1; in main()
37 ("l.srl %0, %1, %2\n\t" in main()
[all …]
H A Dtest_extx.c5 int a, b; in main() local
11 ("l.extbs %0, %1\n\t" in main()
12 : "=r"(a) in main()
15 if (a != result) { in main()
17 return -1; in main()
22 ("l.extbz %0, %1\n\t" in main()
23 : "=r"(a) in main()
26 if (a != result) { in main()
28 return -1; in main()
34 ("l.exths %0, %1\n\t" in main()
[all …]
/qemu/tests/qemu-iotests/
H A D021.out4 == testing writev -P -1 ==
5 -1 is not a valid pattern byte
7 == testing read -P -1 ==
8 -1 is not a valid pattern byte
10 == testing write -P -1 ==
11 -1 is not a valid pattern byte
13 == testing readv -P -1 ==
14 -1 is not a valid pattern byte
16 == testing aio_read -P -1 ==
17 -1 is not a valid pattern byte
[all …]
/qemu/target/mips/tcg/
H A Ddsp_helper.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
34 uint32_t uw[1];
35 int32_t sw[1];
45 uint64_t ul[1];
46 int64_t sl[1];
51 #define MIPSDSP_OVERFLOW_ADD(a, b, c, d) (~((a) ^ (b)) & ((a) ^ (c)) & (d)) argument
52 #define MIPSDSP_OVERFLOW_SUB(a, b, c, d) (((a) ^ (b)) & ((a) ^ (c)) & (d)) argument
62 env->active_tc.DSPControl &= ~(1 << 13); in set_DSPControl_carryflag()
75 filter = ((0x01 << len) - 1) << 24; in set_DSPControl_24()
[all …]
/qemu/target/s390x/tcg/
H A Dvec_int_helper.c21 return !v->doubleword[0] && !v->doubleword[1]; in s390_vec_is_zero()
24 static void s390_vec_and(S390Vector *res, const S390Vector *a, in s390_vec_and() argument
27 res->doubleword[0] = a->doubleword[0] & b->doubleword[0]; in s390_vec_and()
28 res->doubleword[1] = a->doubleword[1] & b->doubleword[1]; in s390_vec_and()
31 static bool s390_vec_equal(const S390Vector *a, const S390Vector *b) in s390_vec_equal() argument
33 return a->doubleword[0] == b->doubleword[0] && in s390_vec_equal()
34 a->doubleword[1] == b->doubleword[1]; in s390_vec_equal()
37 static void s390_vec_shl(S390Vector *d, const S390Vector *a, uint64_t count) in s390_vec_shl() argument
43 d->doubleword[0] = a->doubleword[0]; in s390_vec_shl()
44 d->doubleword[1] = a->doubleword[1]; in s390_vec_shl()
[all …]
/qemu/tests/tcg/s390x/
H A Dadd-logical-with-carry.c23 { "cc0->cc1", {0, 0, 42}, 42, 1, },
27 { "cc1->cc1", {-3, 1, 1}, -1, 1, },
28 { "cc1->cc2", {-3, 1, 2}, 0, 2, },
29 { "cc1->cc3", {-3, 1, -1}, -3, 3, },
31 { "cc2->cc1", {-1, 1, 1}, 2, 1, },
32 { "cc2->cc2", {-1, 1, -1}, 0, 2, },
35 { "cc3->cc1", {-1, 2, 1}, 3, 1, },
36 { "cc3->cc2", {-1, 2, -2}, 0, 2, },
37 { "cc3->cc3", {-1, 2, -1}, 1, 3, },
41 static unsigned long test32rm(unsigned long a, unsigned long b, in test32rm() argument
[all …]
/qemu/target/arm/tcg/
H A Dtranslate-neon.c16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * You should have received a copy of the GNU Lesser General Public
134 if (((vd & 1) * 4 | (vn & 1) * 2 | (vm & 1)) & q) { in do_neon_ddda()
143 tcg_gen_gvec_4_ool(vfp_reg_offset(1, vd), in do_neon_ddda()
144 vfp_reg_offset(1, vn), in do_neon_ddda()
145 vfp_reg_offset(1, vm), in do_neon_ddda()
146 vfp_reg_offset(1, vd), in do_neon_ddda()
164 if (((vd & 1) * 4 | (vn & 1) * 2 | (vm & 1)) & q) { in do_neon_ddda_env()
173 tcg_gen_gvec_4_ptr(vfp_reg_offset(1, vd), in do_neon_ddda_env()
174 vfp_reg_offset(1, vn), in do_neon_ddda_env()
[all …]
H A Dgengvec.c15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * You should have received a copy of the GNU Lesser General Public
44 tcg_debug_assert(vece >= 1 && vece <= 2); in gen_gvec_sqdmulh_qc()
45 gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); in gen_gvec_sqdmulh_qc()
54 tcg_debug_assert(vece >= 1 && vece <= 2); in gen_gvec_sqrdmulh_qc()
55 gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); in gen_gvec_sqrdmulh_qc()
64 tcg_debug_assert(vece >= 1 && vece <= 2); in gen_gvec_sqrdmlah_qc()
65 gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); in gen_gvec_sqrdmlah_qc()
74 tcg_debug_assert(vece >= 1 && vece <= 2); in gen_gvec_sqrdmlsh_qc()
75 gen_gvec_fn3_qc(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, fns[vece - 1]); in gen_gvec_sqrdmlsh_qc()
[all …]
H A Dvec_internal.h13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
29 * so addressing units smaller than that needs a host-endian fixup.
34 * casting the final pointer to a type of size N.
41 #define H4(x) ((x) ^ 1)
51 * and H1_8 so that when a function is being generated from a macro we
67 extern const uint64_t expand_pred_h_data[0x55 + 1];
94 src >>= -shift - 1; in do_sqrshl_bhs()
95 return (src >> 1) + (src & 1); in do_sqrshl_bhs()
114 *sat = 1; in do_sqrshl_bhs()
[all …]
/qemu/include/standard-headers/drm/
H A Ddrm_fourcc.h4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * fourcc code, a Format Modifier may optionally be provided, in order to
43 * Format modifiers are used in conjunction with a fourcc code, forming a
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
61 * match only a single modifier. A modifier must not be a subset of layouts of
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
68 * a canonical pair needs to be defined and used by all drivers. Preferred
104 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ argument
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_mac16.S8 #define mul16(a, b) ((ext16(a) * ext16(b))) argument
29 .macro test_mulxx mulop, comb, s, t, a, b
30 init_reg \comb & 2, \s, \a
31 init_reg \comb & 1, \t, \b
34 assert_acc_value mul16(\a, \b)
37 assert_acc_value mul16(\a, (\b >> 16))
40 assert_acc_value mul16((\a >> 16), \b)
43 assert_acc_value mul16((\a >> 16), (\b >> 16))
51 test_mulxx mul.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f
70 .macro test_mulxxx mulop, comb, s, t, a, b, iv, op
[all …]
/qemu/target/ppc/
H A Dint_helper.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
41 env->so = env->ov = env->ov32 = 1; in helper_update_ov_legacy()
57 overflow = 1; in helper_DIVWEU()
84 ((divisor == -1ull) && (dividend == INT64_MIN)))) { in helper_DIVWE()
85 overflow = 1; in helper_DIVWE()
110 overflow = 1; in helper_DIVDEU()
131 overflow = 1; in helper_DIVDE()
152 * subtract 1 from each byte, and with inverse, check if MSB is set at each
159 /* When you XOR the pattern and there is a match, that byte will be zero */
[all …]
/qemu/hw/dma/
H A Domap_dma.c14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * You should have received a copy of the GNU General Public License along
127 #define TIMEOUT_INTR (1 << 0)
128 #define EVENT_DROP_INTR (1 << 1)
129 #define HALF_FRAME_INTR (1 << 2)
130 #define END_FRAME_INTR (1 << 3)
131 #define LAST_FRAME_INTR (1 << 4)
132 #define END_BLOCK_INTR (1 << 5)
133 #define SYNC (1 << 6)
134 #define END_PKT_INTR (1 << 7)
[all …]
/qemu/target/arm/
H A Dcpregs.h13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * You should have received a copy of the GNU General Public License
51 ARM_CP_CONST = 1 << 4,
53 ARM_CP_64BIT = 1 << 5,
55 * Flag: TB should not be ended after a write to this register
58 ARM_CP_SUPPRESS_TB_END = 1 << 6,
60 * Flag: Permit a register definition to override a previous definition
64 ARM_CP_OVERRIDE = 1 << 7,
71 ARM_CP_ALIAS = 1 << 8,
77 ARM_CP_IO = 1 << 9,
[all …]
/qemu/linux-user/
H A Dmmap.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * You should have received a copy of the GNU General Public License
61 /* Grab lock to make sure things are in a consistent state after fork(). */
83 IntervalTreeNode *i = g_new0(IntervalTreeNode, 1); in shm_region_add()
197 last = start + len - 1; in target_mprotect()
199 host_last = ROUND_UP(last, host_page_size) - 1; in target_mprotect()
207 for (abi_ulong a = host_start; a < start; a += TARGET_PAGE_SIZE) { in target_mprotect() local
208 prot1 |= page_get_flags(a); in target_mprotect()
210 for (abi_ulong a = last; a < host_last; a += TARGET_PAGE_SIZE) { in target_mprotect() local
211 prot1 |= page_get_flags(a + 1); in target_mprotect()
[all …]

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