Lines Matching +full:1 +full:a
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * fourcc code, a Format Modifier may optionally be provided, in order to
43 * Format modifiers are used in conjunction with a fourcc code, forming a
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
61 * match only a single modifier. A modifier must not be a subset of layouts of
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
68 * a canonical pair needs to be defined and used by all drivers. Preferred
104 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ argument
107 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
113 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1…
118 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */
119 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1…
130 /* 1 bpp Red (direct relationship between channel value and brightness) */
131 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1…
143 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
146 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
149 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
164 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian…
165 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian…
166 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian…
167 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian…
169 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
170 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
171 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
172 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
174 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian…
175 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian…
176 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian…
177 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian…
179 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
180 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
181 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
182 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
184 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
185 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
197 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
198 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
199 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
200 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
207 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
208 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
209 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
210 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
216 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 littl…
217 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 littl…
222 * [15:0] sign:exponent:mantissa 1:5:10
227 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 litt…
228 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 litt…
234 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 1…
242 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
243 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endi…
253 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:…
254 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:…
255 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16…
261 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
262 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
263 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
271 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
273 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
275 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
278 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
280 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
284 * 1-plane YUV 4:2:0
287 * These formats can only be used with a non-Linear modifier.
290 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
293 * 2 plane RGB + A
295 * index 1 = A plane, [7:0] A
297 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
298 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
299 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
300 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
301 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
302 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
303 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
304 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
309 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
311 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
313 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
314 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
315 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
316 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
322 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
324 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
331 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
333 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per …
338 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
340 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
345 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
347 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per …
352 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
354 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per …
359 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
366 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
369 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
374 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
377 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
382 * index 1: Cb plane, [7:0] Cb
385 * index 1: Cr plane, [7:0] Cr
388 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) plane…
389 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) plane…
390 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) plane…
391 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) plane…
392 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) plane…
393 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) plane…
394 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) plane…
395 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) plane…
396 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
397 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
403 * Format modifiers describe, typically, a re-ordering or modification
404 * of the data in a plane of an FB. This can be used to express tiled/
405 * swizzled formats, or compression, or a combination of the two.
407 * The upper 8 bits of the format modifier are a vendor-id as assigned
428 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
442 * When adding a new token please document the layout with a code comment,
450 * compatibility, in cases where a vendor-specific definition already exists and
451 * a generic name for it is desired, the common name is a purely symbolic alias
458 * In future cases where a generic layout is identified before merging with a
459 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
462 * apply to a single vendor.
475 * This modifier can be used as a sentinel to terminate the format modifiers
476 * list, or to initialize a variable with an invalid modifier. It might also be
487 * and so might actually result in a tiled framebuffer.
496 * used is out-of-band information carried in an API-specific way (e.g. in a
506 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
508 * a platform-dependent stride. On top of that the memory can apply
513 * cross-driver sharing. It exists since on a given platform it does uniquely
514 * identify the layout in a simple way for i915-specific userspace, which
518 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
523 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
525 * chunks column-major, with a platform-dependent height. On top of that the
531 * cross-driver sharing. It exists since on a given platform it does uniquely
532 * identify the layout in a simple way for i915-specific userspace, which
541 * This is a tiled layout using 4Kb tiles in row-major layout.
547 * either a square block or a 2:1 unit.
558 * the CCS will be plane index 1.
560 * Each CCS tile matches a 1024x512 pixel area of the main surface.
565 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
577 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
578 * main surface. In other words, 4 bits in CCS map to a main surface cache
579 * line pair. The main surface pitch is required to be a multiple of four
588 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
589 * main surface. In other words, 4 bits in CCS map to a main surface cache
590 * line pair. The main surface pitch is required to be a multiple of four
592 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
602 * and at index 1. The clear color is stored at index 2, and the pitch should
610 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
612 * pitch is required to be a multiple of 4 tile widths.
619 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
622 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
631 * outside of the GEM object in a reserved memory area dedicated for the
633 * main surface pitch is required to be a multiple of four Tile 4 widths.
642 * 0 and 1, respectively. The CCS for all planes are stored outside of the
643 * GEM object in a reserved memory area dedicated for the storage of the
645 * pitch is required to be a multiple of four Tile 4 widths.
653 * outside of the GEM object in a reserved memory area dedicated for the
655 * main surface pitch is required to be a multiple of four Tile 4 widths. The
656 * clear color is stored at plane index 1 and the pitch should be 64 bytes
667 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
668 * main surface. In other words, 4 bits in CCS map to a main surface cache
669 * line pair. The main surface pitch is required to be a multiple of four
678 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
679 * main surface. In other words, 4 bits in CCS map to a main surface cache
680 * line pair. The main surface pitch is required to be a multiple of four
682 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
692 * and at index 1. The clear color is stored at index 2, and the pitch should
700 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
702 * pitch is required to be a multiple of 4 tile widths.
712 * 0 and 1, respectively. The CCS for all planes are stored outside of the
713 * GEM object in a reserved memory area dedicated for the storage of the
724 * 0 and 1, respectively. The CCS for all planes are stored outside of the
725 * GEM object in a reserved memory area dedicated for the storage of the
727 * contiguous memory with a size aligned to 64KB
734 * Macroblocks are laid in a Z-shape, and each pixel data is following the
737 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
744 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
749 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
750 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
758 * Refers to a compressed variant of the base format that is compressed.
766 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
795 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
798 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
803 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
815 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
825 * starts at a different base address. Offsets from the base addresses are
832 * the color buffer tiling modifiers defined above. When TS is present it's a
841 #define VIVANTE_MOD_TS_64_4 (1ULL << 48)
848 * Vivante compression modifiers. Those depend on a TS modifier being present
852 #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52)
866 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
874 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
876 * a block depth or height of "4").
889 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
897 * hardware support a block width of two gobs, but it is impractical
905 * 19:12 k Page Kind. This value directly maps to a field in the page
918 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
923 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
927 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
934 * 1 = Desktop GPU and Tegra Xavier+ Layout
939 * 1 = ROP/3D, layout 1, exact compression format implied by Page
978 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
980 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
986 * 1 == TWO_GOBS
1001 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
1023 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1025 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1034 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1037 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1040 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1047 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
1068 * and UV. Some SAND-using hardware stores UV in a separate tiled
1074 * wide, but as this is a 10 bpp format that translates to 96 pixels.
1111 * necessary to reduce the padding. If a hardware block can't do XOR,
1112 * the assumption is that a no-XOR tiling modifier will be created.
1119 * AFBC is a proprietary lossless image compression protocol and format.
1134 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1150 * size (in pixels) must be aligned to a multiple of the superblock size.
1160 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
1171 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
1177 * half of the payload is positioned at a predefined offset from the start
1180 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
1185 * This flag indicates that the payload of each superblock must be stored at a
1192 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
1201 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
1207 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1213 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1219 * can be reduced if a whole superblock is a single color.
1221 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
1226 * Indicates that the buffer is allocated in a layout safe for front-buffer
1229 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1236 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1244 * affects the storage mode of the individual superblocks. Note that even a
1248 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
1253 * AFRC is a proprietary fixed rate image compression protocol and format,
1261 * "coding unit" blocks which are individually compressed to a
1262 * fixed size (in bytes). All coding units within a given plane of a buffer
1277 * to a multiple of the paging tile dimensions.
1292 * 1 SCAN 16 samples 4 samples
1293 * Example: 16x4 luma samples in a 'Y' plane
1294 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1296 * 1 ROT 8 samples 8 samples
1297 * Example: 8x8 luma samples in a 'Y' plane
1298 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1301 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1337 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
1351 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1361 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1367 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1375 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1380 * Amlogic uses a proprietary lossless image compression protocol and format
1414 * - a body content organized in 64x32 superblocks with 4096 bytes per
1416 * - a 32 bytes per 128x64 header block
1420 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1437 * The user-space clients should expect a failure while trying to mmap
1455 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1506 * 1 128x128
1512 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
1514 * Compressed images pad the body to 128-bytes and are immediately followed by a
1531 * software as a single plane. This is modelled after AFBC, a similar
1538 #define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)
1551 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1555 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1585 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1612 * 1 - 256B_2D - 2D block dimensions
1620 #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
1626 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1659 * and prefers the driver provided color. This necessitates doing a fastclear
1660 * eliminate operation before a process transfers control.