Searched +full:16 +full:- +full:bit (Results 1 – 25 of 1077) sorted by relevance
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/linux-5.10/drivers/mtd/nand/raw/ |
D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only 29 {"TC58NVG0S3E 1G 3.3V 8-bit", 32 {"TC58NVG2S0F 4G 3.3V 8-bit", 35 {"TC58NVG2S0H 4G 3.3V 8-bit", 38 {"TC58NVG3S0F 8G 3.3V 8-bit", 41 {"TC58NVG5D2 32G 3.3V 8-bit", 44 {"TC58NVG6D2 64G 3.3V 8-bit", 47 {"SDTNRGAMA 64G 3.3V 8-bit", 50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", 54 {"TH58NVG2S3HBAI4 4G 3.3V 8-bit", [all …]
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/linux-5.10/drivers/staging/sm750fb/ |
D | ddk750_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 7 #define DE_STATE1_DE_ABORT BIT(0) 10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3) 11 #define DE_STATE2_DE_STATUS_BUSY BIT(2) 12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1) 20 #define SYSTEM_CTRL_PCI_BURST BIT(29) 21 #define SYSTEM_CTRL_PCI_MASTER BIT(25) 22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24) 23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23) 24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22) [all …]
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D | sm750_accel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 25 #define DE_SOURCE_WRAP BIT(31) 26 #define DE_SOURCE_X_K1_SHIFT 16 27 #define DE_SOURCE_X_K1_MASK (0x3fff << 16) 28 #define DE_SOURCE_X_K1_MONO_MASK (0x1f << 16) 32 #define DE_DESTINATION_WRAP BIT(31) 33 #define DE_DESTINATION_X_SHIFT 16 34 #define DE_DESTINATION_X_MASK (0x1fff << 16) 38 #define DE_DIMENSION_X_SHIFT 16 39 #define DE_DIMENSION_X_MASK (0x1fff << 16) [all …]
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/linux-5.10/drivers/gpu/drm/mediatek/ |
D | mtk_dpi_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 10 #define EN BIT(0) 13 #define RST BIT(0) 16 #define INT_VSYNC_EN BIT(0) 17 #define INT_VDE_EN BIT(1) 18 #define INT_UNDERFLOW_EN BIT(2) 21 #define INT_VSYNC_STA BIT(0) 22 #define INT_VDE_STA BIT(1) 23 #define INT_UNDERFLOW_STA BIT(2) 26 #define BG_ENABLE BIT(0) [all …]
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/linux-5.10/drivers/media/platform/omap3isp/ |
D | ispreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * TI OMAP3 ISP - Registers definitions 48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1) 58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0) 61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11) 62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10) 63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9) 64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8) 65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7) 66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5) [all …]
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/linux-5.10/include/soc/mscc/ |
D | ocelot_dev.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 15 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 16 #define DEV_CLOCK_CFG_PHY_RST BIT(2) 20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4) 21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3) 22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2) [all …]
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D | ocelot_hsio.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31) 86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30) 87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29) 88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28) 89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27) 96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) 97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16) 98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) 99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15) [all …]
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D | ocelot_ana.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22) 12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21) 13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20) 14 #define ANA_ANAGEFIL_PID_EN BIT(19) 18 #define ANA_ANAGEFIL_VID_EN BIT(13) 27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2) 31 #define ANA_AUTOAGE_AGE_FAST BIT(21) 35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0) 37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1) [all …]
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/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
D | dwxgmac2.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 28 #define XGMAC_CONFIG_JD BIT(16) 29 #define XGMAC_CONFIG_TE BIT(0) 32 #define XGMAC_CONFIG_ARPEN BIT(31) 33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16) 34 #define XGMAC_CONFIG_GPSL_SHIFT 16 38 #define XGMAC_CONFIG_S2KP BIT(11) 39 #define XGMAC_CONFIG_LM BIT(10) 40 #define XGMAC_CONFIG_IPC BIT(9) 41 #define XGMAC_CONFIG_JE BIT(8) [all …]
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/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/ |
D | regs.h | 1 /* SPDX-License-Identifier: ISC */ 28 #define MT_INT_RX_DONE(_n) BIT(_n) 31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4) 33 #define MT_INT_RX_COHERENT BIT(20) 34 #define MT_INT_TX_COHERENT BIT(21) 35 #define MT_INT_MAC_IRQ3 BIT(27) 37 #define MT_INT_MCU_CMD BIT(30) 40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) 41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) 42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) [all …]
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D | mac.h | 1 /* SPDX-License-Identifier: ISC */ 9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16) 10 #define MT_RXD0_NORMAL_IP_SUM BIT(23) 11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) 12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25) 13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26) 14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27) 15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28) 29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23) 30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22) [all …]
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/linux-5.10/drivers/net/ethernet/marvell/ |
D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 131 /* B0_CTST 16 bit Control/Status register */ 133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */ 134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */ 135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */ 138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */ 142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ 148 /* B0_LED 8 Bit LED register */ 149 /* Bit 7.. 2: reserved */ 153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ [all …]
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/linux-5.10/drivers/gpu/drm/vc4/ |
D | vc4_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright © 2014-2015 Broadcom 27 ('D' << 16)) 33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) 34 # define V3D_IDENT1_NSEM_SHIFT 16 47 # define V3D_L2CACTL_L2CCLR BIT(2) 48 # define V3D_L2CACTL_L2CDIS BIT(1) 49 # define V3D_L2CACTL_L2CENA BIT(0) 54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) 55 # define V3D_SLCACTL_T0CC_SHIFT 16 [all …]
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/linux-5.10/drivers/media/platform/vsp1/ |
D | vsp1_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 3 * vsp1_regs.h -- R-Car VSP1 Registers Definitions 13 /* ----------------------------------------------------------------------------- 18 #define VI6_CMD_UPDHDR BIT(4) 19 #define VI6_CMD_STRCMD BIT(0) 28 #define VI6_SRESET_SRTS(n) BIT(n) 31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28) 32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8) 35 #define VI6_WFP_IRQ_ENB_DFEE BIT(1) 36 #define VI6_WFP_IRQ_ENB_FREE BIT(0) [all …]
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/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/ |
D | mac.h | 1 /* SPDX-License-Identifier: ISC */ 11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16) 14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16) 15 #define MT_RXD0_NORMAL_IP_SUM BIT(23) 16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) 17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25) 18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26) 19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27) 20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28) 36 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23) [all …]
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/linux-5.10/drivers/gpu/drm/v3d/ |
D | v3d_regs.h | 1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2017-2018 Broadcom */ 30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19) 31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18) 32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17) 33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16) 44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8) 60 # define V3D_HUB_INT_MMU_WRV BIT(5) 61 # define V3D_HUB_INT_MMU_PTI BIT(4) 62 # define V3D_HUB_INT_MMU_CAP BIT(3) [all …]
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/linux-5.10/drivers/infiniband/hw/ocrdma/ |
D | ocrdma_sli.h | 3 * Copyright (C) 2012-2015 Emulex. All rights reserved. 16 * - Redistributions of source code must retain the above copyright notice, 19 * - Redistributions in binary form must reproduce the above copyright 36 * linux-drivers@emulex.com 77 OCRDMA_CMD_QUERY_NSMR = 16, 122 #define OCRDMA_MAX_SGID 16 139 OCRDMA_DB_SQ_SHIFT = 16, 149 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 150 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */ 151 /* qid #2 msbits at 12-11 */ [all …]
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/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/ |
D | mac.h | 1 /* SPDX-License-Identifier: ISC */ 13 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16) 14 #define MT_RXD0_NORMAL_IP_SUM BIT(23) 15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) 30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11) 31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12) 32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13) 33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14) 34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15) 35 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16) [all …]
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/linux-5.10/drivers/gpu/drm/arm/display/komeda/d71/ |
D | d71_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 46 #define BLK_CTRL_EN BIT(0) 48 #define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16)) 49 #define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16)) 50 #define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16)) 56 #define AD_AEN BIT(0) 57 #define AD_YT BIT(1) 58 #define AD_BS BIT(2) 59 #define AD_WB BIT(3) 60 #define AD_TH BIT(4) [all …]
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/linux-5.10/drivers/gpu/drm/fsl-dcu/ |
D | fsl_dcu_drm_drv.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 19 #define DCU_MODE_RASTER_EN BIT(14) 28 #define DCU_BGND_R(x) ((x) << 16) 33 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) 34 /*Regisiter value 1/16 of horizontal resolution*/ 48 #define DCU_SYN_POL_INV_PXCK BIT(6) 49 #define DCU_SYN_POL_NEG BIT(5) 50 #define DCU_SYN_POL_INV_VS_LOW BIT(1) 51 #define DCU_SYN_POL_INV_HS_LOW BIT(0) 54 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) [all …]
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/linux-5.10/drivers/media/platform/ti-vpe/ |
D | vpe_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 26 #define VPE_PID_FUNC_SHIFT 16 51 #define VPE_INT0_LIST0_COMPLETE BIT(0) 52 #define VPE_INT0_LIST0_NOTIFY BIT(1) 53 #define VPE_INT0_LIST1_COMPLETE BIT(2) 54 #define VPE_INT0_LIST1_NOTIFY BIT(3) 55 #define VPE_INT0_LIST2_COMPLETE BIT(4) 56 #define VPE_INT0_LIST2_NOTIFY BIT(5) 57 #define VPE_INT0_LIST3_COMPLETE BIT(6) 58 #define VPE_INT0_LIST3_NOTIFY BIT(7) [all …]
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/linux-5.10/drivers/net/dsa/ |
D | qca8k.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 34 #define QCA8K_PORT_PAD_RGMII_EN BIT(26) 40 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) 41 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) 43 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) 45 #define QCA8K_MODULE_EN_MIB BIT(0) 47 #define QCA8K_MIB_FLUSH BIT(24) 48 #define QCA8K_MIB_CPU_KEEP BIT(20) 49 #define QCA8K_MIB_BUSY BIT(17) [all …]
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/linux-5.10/drivers/net/wireless/ath/wil6210/ |
D | txrx_edma.h | 1 /* SPDX-License-Identifier: ISC */ 3 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved. 25 #define WIL_EDMA_AGG_WATERMARK_POS (16) 37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1)) 38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1)) 40 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11) 49 #define WIL_RX_EDMA_MID_VALID_BIT BIT(20) 51 #define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS 16 75 /* Enhanced Rx descriptor - MAC part 80 * bit 0..15 : Buffer ID [all …]
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/linux-5.10/drivers/net/phy/mscc/ |
D | mscc_mac.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 77 #define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA BIT(0) 78 #define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA BIT(4) 79 #define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST BIT(8) 80 #define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST BIT(12) 81 #define MSCC_MAC_CFG_ENA_CFG_RX_ENA BIT(16) 82 #define MSCC_MAC_CFG_ENA_CFG_TX_ENA BIT(20) 86 #define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE BIT(16) 87 #define MSCC_MAC_CFG_MODE_CFG_TUNNEL_PAUSE_FRAMES BIT(14) 90 #define MSCC_MAC_CFG_MODE_CFG_MAC_IPG_CFG BIT(6) [all …]
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/linux-5.10/include/linux/mfd/syscon/ |
D | imx6q-iomuxc-gpr.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 60 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16) 61 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16) 62 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16) 63 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16) 64 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16) 69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7) 71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7) 72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6) 74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6) [all …]
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