drm/fsl-dcu/fsl_dcu_drm_drv.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 #define DCU_MODE_RASTER_EN		BIT(14)
28 #define DCU_BGND_R(x)			((x) << 16)
33 #define DCU_DISP_SIZE_DELTA_Y(x)	((x) << 16)
34 /*Regisiter value 1/16 of horizontal resolution*/
48 #define DCU_SYN_POL_INV_PXCK		BIT(6)
49 #define DCU_SYN_POL_NEG			BIT(5)
50 #define DCU_SYN_POL_INV_VS_LOW		BIT(1)
51 #define DCU_SYN_POL_INV_HS_LOW		BIT(0)
54 #define DCU_THRESHOLD_LS_BF_VS(x)	((x) << 16)
62 #define DCU_INT_STATUS_VSYNC		BIT(0)
63 #define DCU_INT_STATUS_UNDRUN		BIT(1)
64 #define DCU_INT_STATUS_LSBFVS		BIT(2)
65 #define DCU_INT_STATUS_VBLANK		BIT(3)
66 #define DCU_INT_STATUS_CRCREADY		BIT(4)
67 #define DCU_INT_STATUS_CRCOVERFLOW	BIT(5)
68 #define DCU_INT_STATUS_P1FIFOLO		BIT(6)
69 #define DCU_INT_STATUS_P1FIFOHI		BIT(7)
70 #define DCU_INT_STATUS_P2FIFOLO		BIT(8)
71 #define DCU_INT_STATUS_P2FIFOHI		BIT(9)
72 #define DCU_INT_STATUS_PROGEND		BIT(10)
73 #define DCU_INT_STATUS_IPMERROR		BIT(11)
74 #define DCU_INT_STATUS_LYRTRANS		BIT(12)
75 #define DCU_INT_STATUS_DMATRANS		BIT(14)
76 #define DCU_INT_STATUS_P3FIFOLO		BIT(16)
77 #define DCU_INT_STATUS_P3FIFOHI		BIT(17)
78 #define DCU_INT_STATUS_P4FIFOLO		BIT(18)
79 #define DCU_INT_STATUS_P4FIFOHI		BIT(19)
80 #define DCU_INT_STATUS_P1EMPTY		BIT(26)
81 #define DCU_INT_STATUS_P2EMPTY		BIT(27)
82 #define DCU_INT_STATUS_P3EMPTY		BIT(28)
83 #define DCU_INT_STATUS_P4EMPTY		BIT(29)
86 #define DCU_INT_MASK_VSYNC		BIT(0)
87 #define DCU_INT_MASK_UNDRUN		BIT(1)
88 #define DCU_INT_MASK_LSBFVS		BIT(2)
89 #define DCU_INT_MASK_VBLANK		BIT(3)
90 #define DCU_INT_MASK_CRCREADY		BIT(4)
91 #define DCU_INT_MASK_CRCOVERFLOW	BIT(5)
92 #define DCU_INT_MASK_P1FIFOLO		BIT(6)
93 #define DCU_INT_MASK_P1FIFOHI		BIT(7)
94 #define DCU_INT_MASK_P2FIFOLO		BIT(8)
95 #define DCU_INT_MASK_P2FIFOHI		BIT(9)
96 #define DCU_INT_MASK_PROGEND		BIT(10)
97 #define DCU_INT_MASK_IPMERROR		BIT(11)
98 #define DCU_INT_MASK_LYRTRANS		BIT(12)
99 #define DCU_INT_MASK_DMATRANS		BIT(14)
100 #define DCU_INT_MASK_P3FIFOLO		BIT(16)
101 #define DCU_INT_MASK_P3FIFOHI		BIT(17)
102 #define DCU_INT_MASK_P4FIFOLO		BIT(18)
103 #define DCU_INT_MASK_P4FIFOHI		BIT(19)
104 #define DCU_INT_MASK_P1EMPTY		BIT(26)
105 #define DCU_INT_MASK_P2EMPTY		BIT(27)
106 #define DCU_INT_MASK_P3EMPTY		BIT(28)
107 #define DCU_INT_MASK_P4EMPTY		BIT(29)
112 #define DCU_UPDATE_MODE_MODE		BIT(31)
113 #define DCU_UPDATE_MODE_READREG		BIT(30)
117 #define DCU_CTRLDESCLN(layer, reg)	(0x200 + (reg - 1) * 4 + (layer) * 0x40)
119 #define DCU_LAYER_HEIGHT(x)		((x) << 16)
122 #define DCU_LAYER_POSY(x)		((x) << 16)
125 #define DCU_LAYER_EN			BIT(31)
126 #define DCU_LAYER_TILE_EN		BIT(30)
127 #define DCU_LAYER_DATA_SEL_CLUT		BIT(29)
128 #define DCU_LAYER_SAFETY_EN		BIT(28)
130 #define DCU_LAYER_BPP(x)		((x) << 16)
131 #define DCU_LAYER_RLE_EN		BIT(15)
133 #define DCU_LAYER_BB_ON			BIT(2)
138 #define DCU_LAYER_CKMAX_R(x)		((x) << 16)
142 #define DCU_LAYER_CKMIN_R(x)		((x) << 16)
146 #define DCU_LAYER_TILE_VER(x)		((x) << 16)
153 #define DCU_LAYER_POST_SKIP(x)		((x) << 16)