Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
45 #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
46 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
48 #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24)
49 #define MT_WPDMA_GLO_CFG_FORCE_TX_EOF BIT(25)
50 #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
57 #define MT_WPDMA_DEBUG_SEL BIT(27)
75 #define MT_SCH_4_BYPASS BIT(5)
76 #define MT_SCH_4_RESET BIT(8)
99 #define MT_MCU_DEBUG_RESET_PSE BIT(0)
100 #define MT_MCU_DEBUG_RESET_PSE_S BIT(1)
105 #define MT_PSE_FC_P0_MAX_QUOTA GENMASK(27, 16)
116 #define MT_FC_RSV_COUNT_0_P1 GENMASK(27, 16)
120 #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q1 GENMASK(27, 16)
127 #define MT_PSE_RTA_REDIRECT_EN BIT(7)
129 #define MT_PSE_RTA_WRITE BIT(16)
130 #define MT_PSE_RTA_BUSY BIT(31)
142 #define MT_AGC_41_RSSI_0 GENMASK(23, 16)
153 #define MT_RXTD_13_ACI_TH_EN BIT(0)
163 #define MT_PHYCTRL_2_STATUS_RESET BIT(6)
164 #define MT_PHYCTRL_2_STATUS_EN BIT(7)
167 #define MT_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)
171 #define MT_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)
178 #define MT_AGG_ARCR_INIT_RATE1 BIT(0)
179 #define MT_AGG_ARCR_FB_SGI_DISABLE BIT(1)
180 #define MT_AGG_ARCR_RATE8_DOWN_WRAP BIT(2)
182 #define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16)
183 #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19)
196 #define MT_AGG_LIMIT_AC(_n) GENMASK(((_n) + 1) * 8 - 1, (_n) * 8)
203 #define MT_AGG_PCR_MM BIT(16)
204 #define MT_AGG_PCR_GF BIT(17)
205 #define MT_AGG_PCR_BW40 BIT(18)
206 #define MT_AGG_PCR_RIFS BIT(19)
207 #define MT_AGG_PCR_BW80 BIT(20)
208 #define MT_AGG_PCR_BW160 BIT(21)
209 #define MT_AGG_PCR_ERP BIT(22)
219 #define MT_AGG_CONTROL_NO_BA_RULE BIT(0)
220 #define MT_AGG_CONTROL_NO_BA_AR_RULE BIT(1)
221 #define MT_AGG_CONTROL_CFEND_SPE_EN BIT(3)
223 #define MT_AGG_CONTROL_BAR_SPE_EN BIT(19)
240 #define MT_DMA_DCR0_DAMSDU BIT(16)
241 #define MT_DMA_DCR0_RX_VEC_DROP BIT(17)
248 #define MT_DMA_FQCR0_TARGET_QID GENMASK(20, 16)
251 #define MT_DMA_FQCR0_MODE BIT(29)
252 #define MT_DMA_FQCR0_STATUS BIT(30)
253 #define MT_DMA_FQCR0_BUSY BIT(31)
260 #define MT_DMA_TCFR_TXS_AGGR_TIMEOUT GENMASK(27, 16)
261 #define MT_DMA_TCFR_TXS_QUEUE BIT(14)
276 #define MT_WMM_CWMAX_SHIFT(_n) (((_n) & 1) * 16)
284 #define MT_WF_ARB_RQCR_RX_START BIT(0)
285 #define MT_WF_ARB_RQCR_RXV_START BIT(4)
286 #define MT_WF_ARB_RQCR_RXV_R_EN BIT(7)
287 #define MT_WF_ARB_RQCR_RXV_T_EN BIT(8)
292 #define MT_ARB_SCR_TX_DISABLE BIT(8)
293 #define MT_ARB_SCR_RX_DISABLE BIT(9)
294 #define MT_ARB_SCR_BCNQ_EMPTY_SKIP BIT(28)
295 #define MT_ARB_SCR_TTTT_BTIM_PRIO BIT(29)
296 #define MT_ARB_SCR_TBTT_BCN_PRIO BIT(30)
297 #define MT_ARB_SCR_TBTT_BCAST_PRIO BIT(31)
313 #define MT_WF_ARB_BCN_START_BSSn(n) BIT(0 + (n))
314 #define MT_WF_ARB_BCN_START_T_PRE_TTTT BIT(10)
315 #define MT_WF_ARB_BCN_START_T_TTTT BIT(11)
316 #define MT_WF_ARB_BCN_START_T_PRE_TBTT BIT(12)
317 #define MT_WF_ARB_BCN_START_T_TBTT BIT(13)
318 #define MT_WF_ARB_BCN_START_T_SLOT_IDLE BIT(14)
319 #define MT_WF_ARB_BCN_START_T_TX_START BIT(15)
320 #define MT_WF_ARB_BCN_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
323 #define MT_WF_ARB_BCN_FLUSH_BSSn(n) BIT(0 + (n))
324 #define MT_WF_ARB_BCN_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
327 #define MT_WF_ARB_CAB_START_BSSn(n) BIT(0 + (n))
328 #define MT_WF_ARB_CAB_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
331 #define MT_WF_ARB_CAB_FLUSH_BSSn(n) BIT(0 + (n))
332 #define MT_WF_ARB_CAB_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
339 #define MT_WF_ARB_CAB_COUNT_B0_SHIFT(n) (((n) > 12 ? (n) - 12 : \
340 ((n) > 4 ? (n) - 4 : \
344 #define MT_TX_ABORT_EN BIT(0)
354 #define MT_TMAC_TCR_RTS_SIGTA BIT(14)
355 #define MT_TMAC_TCR_LDPC_OFS BIT(15)
356 #define MT_TMAC_TCR_TX_STREAMS GENMASK(17, 16)
358 #define MT_TMAC_TCR_SCH_DET_PER_IOD BIT(20)
359 #define MT_TMAC_TCR_DCH_DET_DISABLE BIT(21)
360 #define MT_TMAC_TCR_TX_RIFS BIT(22)
361 #define MT_TMAC_TCR_RX_RIFS_MODE BIT(23)
362 #define MT_TMAC_TCR_TXOP_TBTT_CTL BIT(24)
363 #define MT_TMAC_TCR_TBTT_TX_STOP_CTL BIT(25)
364 #define MT_TMAC_TCR_TXOP_BURST_STOP BIT(26)
365 #define MT_TMAC_TCR_RDG_RA_MODE BIT(27)
366 #define MT_TMAC_TCR_RDG_RESP BIT(29)
367 #define MT_TMAC_TCR_RDG_NO_PENDING BIT(30)
368 #define MT_TMAC_TCR_SMOOTHING BIT(31)
373 #define MT_WMM_TXOP_SHIFT(_n) (((_n) & 1) * 16)
379 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
390 #define MT_IFS_SIFS GENMASK(22, 16)
395 #define MT_TMAC_PCR_RATE_FIXED BIT(15)
396 #define MT_TMAC_PCR_ANT_ID GENMASK(21, 16)
397 #define MT_TMAC_PCR_ANT_ID_SEL BIT(22)
398 #define MT_TMAC_PCR_SPE_EN BIT(23)
406 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
407 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
408 #define MT_WF_RFCR_DROP_VERSION BIT(3)
409 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
410 #define MT_WF_RFCR_DROP_MCAST BIT(5)
411 #define MT_WF_RFCR_DROP_BCAST BIT(6)
412 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
413 #define MT_WF_RFCR_DROP_A3_MAC BIT(8)
414 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
415 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
416 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
417 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
418 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
419 #define MT_WF_RFCR_DROP_CTS BIT(14)
420 #define MT_WF_RFCR_DROP_RTS BIT(15)
421 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
422 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
423 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
424 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
425 #define MT_WF_RFCR_DROP_NDPA BIT(20)
426 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
430 #define MT_BSSID1_VALID BIT(16)
435 #define MT_MAC_ADDR1_VALID BIT(16)
440 #define MT_BA_CONTROL_1_TID GENMASK(19, 16)
441 #define MT_BA_CONTROL_1_IGNORE_TID BIT(20)
442 #define MT_BA_CONTROL_1_IGNORE_ALL BIT(21)
443 #define MT_BA_CONTROL_1_RESET BIT(22)
446 #define MT_WF_RMACDR_TSF_PROBERSP_DIS BIT(0)
447 #define MT_WF_RMACDR_TSF_TIM BIT(4)
449 #define MT_WF_RMACDR_CHECK_HTC_BY_RATE BIT(26)
450 #define MT_WF_RMACDR_MAXLEN_20BIT BIT(30)
455 #define MT_WF_RMAC_RMCR_SMPS_RTS BIT(25)
473 #define MT_WTBL_UPDATE_WTBL2 BIT(11)
474 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
475 #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13)
476 #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14)
477 #define MT_WTBL_UPDATE_RX_COUNT_CLEAR BIT(15)
478 #define MT_WTBL_UPDATE_BUSY BIT(16)
481 #define MT_WTBL_RMVTCR_RX_MV_MODE BIT(23)
501 #define MT_TBTT_DTIM_PERIOD GENMASK(23, 16)
504 #define MT_TBTT_CAL_ENABLE BIT(31)
509 #define MT_LPON_SBTOR_SUB_BSS_EN BIT(29)
518 #define MT_HW_INT3_TBTT0 BIT(15)
519 #define MT_HW_INT3_PRE_TBTT0 BIT(31)
536 #define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16)
549 #define MT_MIB_CTL_CCA_NAV_TX GENMASK(16, 14)
551 #define MT_MIB_CTL_READ_CLR_DIS BIT(31)
558 #define MT_MIB_STAT_PSCCA MT_MIB_STAT(16)
579 #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))
580 #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n)))
581 #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n)))
582 #define MT_LED_CTRL_TX_MANUAL_BLINK(_n) BIT(3 + (8 * (_n)))
583 #define MT_LED_CTRL_TX_OVER_BLINK(_n) BIT(5 + (8 * (_n)))
584 #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n)))
589 #define MT_LED_STATUS_ON GENMASK(23, 16)
599 #define MT_CLIENT_RESET_TX_R_E_1 BIT(16)
600 #define MT_CLIENT_RESET_TX_R_E_2 BIT(17)
601 #define MT_CLIENT_RESET_TX_R_E_1_S BIT(20)
602 #define MT_CLIENT_RESET_TX_R_E_2_S BIT(21)
607 #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30)
614 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
615 #define MT_EFUSE_CTRL_VALID BIT(29)
616 #define MT_EFUSE_CTRL_KICK BIT(30)
617 #define MT_EFUSE_CTRL_SEL BIT(31)
630 #define MT_WTBL2_SIZE (16 * 4)
632 #define MT_WTBL3_SIZE (16 * 4)
638 #define MT_WTBL1_W0_MUAR_IDX GENMASK(21, 16)
639 #define MT_WTBL1_W0_RX_CHECK_A1 BIT(22)
641 #define MT_WTBL1_W0_RX_CHECK_KEY_IDX BIT(25)
642 #define MT_WTBL1_W0_RX_KEY_VALID BIT(26)
643 #define MT_WTBL1_W0_RX_IK_VALID BIT(27)
644 #define MT_WTBL1_W0_RX_VALID BIT(28)
645 #define MT_WTBL1_W0_RX_CHECK_A2 BIT(29)
646 #define MT_WTBL1_W0_RX_DATA_VALID BIT(30)
647 #define MT_WTBL1_W0_WRITE_BURST BIT(31)
653 #define MT_WTBL1_W2_EVEN_PN BIT(7)
654 #define MT_WTBL1_W2_TO_DS BIT(8)
655 #define MT_WTBL1_W2_FROM_DS BIT(9)
656 #define MT_WTBL1_W2_HEADER_TRANS BIT(10)
658 #define MT_WTBL1_W2_PWR_MGMT BIT(14)
659 #define MT_WTBL1_W2_RDG BIT(15)
660 #define MT_WTBL1_W2_RTS BIT(16)
661 #define MT_WTBL1_W2_CFACK BIT(17)
662 #define MT_WTBL1_W2_RDG_BA BIT(18)
663 #define MT_WTBL1_W2_SMPS BIT(19)
664 #define MT_WTBL1_W2_TXS_BAF_REPORT BIT(20)
665 #define MT_WTBL1_W2_DYN_BW BIT(21)
666 #define MT_WTBL1_W2_LDPC BIT(22)
667 #define MT_WTBL1_W2_ITXBF BIT(23)
668 #define MT_WTBL1_W2_ETXBF BIT(24)
669 #define MT_WTBL1_W2_TXOP_PS BIT(25)
670 #define MT_WTBL1_W2_MESH BIT(26)
671 #define MT_WTBL1_W2_QOS BIT(27)
672 #define MT_WTBL1_W2_HT BIT(28)
673 #define MT_WTBL1_W2_VHT BIT(29)
674 #define MT_WTBL1_W2_ADMISSION_CONTROL BIT(30)
675 #define MT_WTBL1_W2_GROUP_ID BIT(31)
679 #define MT_WTBL1_W3_WTBL4_FRAME_ID GENMASK(26, 16)
680 #define MT_WTBL1_W3_CHECK_PER BIT(27)
681 #define MT_WTBL1_W3_KEEP_I_PSM BIT(28)
682 #define MT_WTBL1_W3_I_PSM BIT(29)
683 #define MT_WTBL1_W3_POWER_SAVE BIT(30)
684 #define MT_WTBL1_W3_SKIP_TX BIT(31)
687 #define MT_WTBL1_W4_WTBL3_ENTRY_ID GENMASK(16, 11)
694 #define MT_WTBL2_W1_NON_QOS_SEQNO GENMASK(27, 16)
702 #define MT_WTBL2_W3_TID4_SN GENMASK(27, 16)
710 #define MT_WTBL2_W5_FAIL_COUNT_RATE1 GENAMSK(31, 16)
714 #define MT_WTBL2_W6_TX_COUNT_RATE4 GENMASK(23, 16)
718 #define MT_WTBL2_W7_FAIL_COUNT_CUR_BW GENMASK(31, 16)
721 #define MT_WTBL2_W8_FAIL_COUNT_OTHER_BW GENMASK(31, 16)
724 #define MT_WTBL2_W9_SPATIAL_EXT BIT(5)
729 #define MT_WTBL2_W9_SHORT_GI_20 BIT(16)
730 #define MT_WTBL2_W9_SHORT_GI_40 BIT(17)
731 #define MT_WTBL2_W9_SHORT_GI_80 BIT(18)
732 #define MT_WTBL2_W9_SHORT_GI_160 BIT(19)
743 #define MT_WTBL2_W11_RATE5 GENMASK(27, 16)
752 #define MT_WTBL2_W13_AVG_RCPI2 GENAMSK(23, 16)
758 #define MT_WTBL2_W14_CC_NOISE_SEL BIT(15)
766 #define MT_WTBL1_OR_PSM_WRITE BIT(31)