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/linux-6.15/drivers/gpu/drm/display/
Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
35 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
49 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
50 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
55 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
110 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
111 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
112 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
[all …]
/linux-6.15/drivers/gpu/drm/i915/display/
Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
24 /* from BPP 4 to 12 in steps of 0.5 */
67 { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
90 { 12, 11, 11, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 5,
92 { 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6,
94 { 12, 12, 12, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7,
96 { 12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7,
98 { 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8,
100 { 15, 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 9,
144 { 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11,
[all …]
/linux-6.15/arch/powerpc/crypto/
Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
15 # 2. c += d; b ^= c; b <<<= 12;
20 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 12
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
207 vpermxor 12, 12, 0, 25
208 vpermxor 13, 13, 1, 25
216 vadduwm 8, 8, 12
[all …]
/linux-6.15/drivers/phy/rockchip/
Dphy-rockchip-samsung-dcphy.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
8 #include <dt-bindings/phy/phy.h>
73 * The selection between the 400-based or 200-based values for REG_400M
77 #define REG_325M_MASK GENMASK(14, 12)
134 #define PLL_EN BIT(12)
144 #define MRR_MASK GENMASK(13, 8)
167 #define EDGE_CON(x) FIELD_PREP(GENMASK(14, 12), x)
176 #define HSTX_CLK_SEL BIT(12)
189 #define SKEW_CAL_RUN_TIME(x) FIELD_PREP(GENMASK(15, 12), x)
[all …]
/linux-6.15/drivers/clk/rockchip/
Drst-rk3576.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
49 RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
50 RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
61 RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12),
75 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
85 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
86 RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
91 RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
92 RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1),
[all …]
/linux-6.15/sound/soc/codecs/
Drt5640.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
22 /* I/O - Output */
27 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
78 /* Format - ADC/DAC */
[all …]
Drt5651.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
[all …]
Drt5616.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5616.h -- RT5616 ALSA SoC audio driver
17 /* I/O - Output */
21 /* I/O - Input */
24 /* I/O - ADC/DAC/DMIC */
28 /* Mixer - D-D */
33 /* Mixer - ADC */
38 /* Mixer - DAC */
57 /* Format - ADC/DAC */
62 /* Function - Analog */
[all …]
Drt5645.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
47 /* Mixer - PDM */
49 /* Mixer - ADC */
54 /* Mixer - DAC */
92 /* Format - ADC/DAC */
[all …]
Drt5670.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5670.h -- RT5670 ALSA SoC audio driver
17 /* I/O - Output */
20 /* I/O - Input */
26 /* I/O - ADC/DAC/DMIC */
34 /* Mixer - D-D */
47 /* Mixer - PDM */
56 /* Mixer - ADC */
61 /* Mixer - DAC */
77 /* Format - ADC/DAC */
[all …]
Drt5665.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
30 /* I/O - Input */
36 /* I/O - Speaker */
44 /* I/O - ADC/DAC/DMIC */
58 /* Mixer - D-D */
70 /* Mixer - PDM */
76 /* Mixer - ADC */
88 /* Mixer - DAC */
[all …]
Drt5659.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5659.h -- RT5659/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
31 /* I/O - Input */
36 /* I/O - Speaker */
42 /* I/O - Sidetone */
44 /* I/O - ADC/DAC/DMIC */
56 /* Mixer - D-D */
65 /* Mixer - PDM */
73 /* Mixer - ADC */
[all …]
Drt1015.h1 // SPDX-License-Identifier: GPL-2.0
3 // rt1015.h -- RT1015 ALSA SoC audio amplifier driver
188 #define RT1015_PLL_SEL_MASK (0x1 << 13)
189 #define RT1015_PLL_SEL_SFT 13
190 #define RT1015_PLL_SEL_PLL_SRC2 (0x0 << 13)
191 #define RT1015_PLL_SEL_BCLK (0x1 << 13)
197 #define RT1015_PLL_M_MASK (RT1015_PLL_M_MAX << 12)
198 #define RT1015_PLL_M_SFT 12
233 #define RT1015_DAC_CLK (0x1 << 13)
234 #define RT1015_DAC_CLK_BIT 13
[all …]
/linux-6.15/arch/arm64/crypto/
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
37 * The SHA-512 round constants
111 ld1 {v8.2d-v11.2d}, [x0]
115 ld1 {v20.2d-v23.2d}, [x3], #64
118 0: ld1 {v12.2d-v15.2d}, [x1], #64
119 ld1 {v16.2d-v19.2d}, [x1], #64
138 // v0 ab cd -- ef gh ab
139 // v1 cd -- ef gh ab cd
[all …]
/linux-6.15/drivers/pinctrl/mediatek/
Dpinctrl-mt2712.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include "pinctrl-mtk-common.h"
17 #include "pinctrl-mtk-mt2712.h"
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
23 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
30 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
46 MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
56 MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
[all …]
/linux-6.15/lib/crypto/
Dchacha.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 WARN_ON_ONCE(nrounds != 20 && nrounds != 12); in chacha_permute()
24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
35 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 8); in chacha_permute()
[all …]
Dblake2s-generic.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
[all …]
/linux-6.15/drivers/pinctrl/stm32/
Dpinctrl-stm32mp135.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
10 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH1_MII_CRS"),
23 STM32_FUNCTION(13, "ETH2_MII_CRS"),
35 STM32_FUNCTION(12, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
46 STM32_FUNCTION(12, "ETH1_MDIO"),
59 STM32_FUNCTION(12, "ETH1_MII_COL"),
60 STM32_FUNCTION(13, "ETH2_MII_COL"),
72 STM32_FUNCTION(12, "ETH2_PPS_OUT"),
[all …]
Dpinctrl-stm32h743.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
24 STM32_FUNCTION(12, "ETH_MII_CRS"),
39 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
53 STM32_FUNCTION(12, "ETH_MDIO"),
54 STM32_FUNCTION(13, "MDIOS_MDIO"),
69 STM32_FUNCTION(12, "ETH_MII_COL"),
82 STM32_FUNCTION(13, "OTG_HS_SOF"),
110 STM32_FUNCTION(12, "MDIOS_MDC"),
111 STM32_FUNCTION(13, "TIM1_BKIN_COMP12"),
[all …]
/linux-6.15/drivers/clk/renesas/
Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
136 BUS_MSTOP(10, BIT(12))),
146 BUS_MSTOP(2, BIT(13))),
150 BUS_MSTOP(11, BIT(13))),
156 BUS_MSTOP(12, BIT(0))),
159 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
161 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
[all …]
/linux-6.15/include/linux/mfd/wm831x/
Dregulator.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
14 * R16462 (0x404E) - Current Sink 1
26 #define WM831X_CS1_SLPENA_SHIFT 12 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
29 #define WM831X_CS1_OFF_RAMP_SHIFT 10 /* CS1_OFF_RAMP - [11:10] */
30 #define WM831X_CS1_OFF_RAMP_WIDTH 2 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
32 #define WM831X_CS1_ON_RAMP_SHIFT 8 /* CS1_ON_RAMP - [9:8] */
33 #define WM831X_CS1_ON_RAMP_WIDTH 2 /* CS1_ON_RAMP - [9:8] */
[all …]
/linux-6.15/arch/x86/crypto/
Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
4 * Copyright (C) 2017-2019 Samuel Neves <sneves@dei.uc.pt>. All Rights Reserved.
22 .byte 0, 2, 4, 6, 1, 3, 5, 7, 14, 8, 10, 12, 15, 9, 11, 13
23 .byte 14, 4, 9, 13, 10, 8, 15, 6, 5, 1, 0, 11, 3, 12, 2, 7
24 .byte 11, 12, 5, 15, 8, 0, 2, 13, 9, 10, 3, 7, 4, 14, 6, 1
25 .byte 7, 3, 13, 11, 9, 1, 12, 14, 15, 2, 5, 4, 8, 6, 10, 0
26 .byte 9, 5, 2, 10, 0, 7, 4, 15, 3, 14, 11, 6, 13, 1, 12, 8
27 .byte 2, 6, 0, 8, 12, 10, 11, 3, 1, 4, 7, 15, 9, 13, 5, 14
28 .byte 12, 1, 14, 4, 5, 15, 13, 10, 8, 0, 6, 9, 11, 7, 3, 2
[all …]
/linux-6.15/crypto/
Dblake2b_generic.c1 // SPDX-License-Identifier: (GPL-2.0-only OR Apache-2.0)
11 * - CC0 1.0 Universal : http://creativecommons.org/publicdomain/zero/1.0
12 * - OpenSSL license : https://www.openssl.org/source/license.html
13 * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0
25 static const u8 blake2b_sigma[12][16] = {
26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
[all …]
/linux-6.15/arch/mips/crypto/
Dchacha-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2016-2018 René van Dorst <opensource@vdorst.com>. All Rights Reserved.
4 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
84 x(12); \
85 x(13); \
92 x(13); \
93 x(12); \
118 #define PLUS_ONE_11 12
119 #define PLUS_ONE_12 13
129 .if (x != 12); \
[all …]

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