1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2H(P) CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLVDO, 32 33 /* Internal Core Clocks */ 34 CLK_PLLCM33_DIV4, 35 CLK_PLLCM33_DIV4_PLLCM33, 36 CLK_PLLCM33_DIV16, 37 CLK_PLLCLN_DIV2, 38 CLK_PLLCLN_DIV8, 39 CLK_PLLCLN_DIV16, 40 CLK_PLLDTY_ACPU, 41 CLK_PLLDTY_ACPU_DIV2, 42 CLK_PLLDTY_ACPU_DIV4, 43 CLK_PLLDTY_DIV16, 44 CLK_PLLDTY_RCPU, 45 CLK_PLLDTY_RCPU_DIV4, 46 CLK_PLLVDO_CRU0, 47 CLK_PLLVDO_CRU1, 48 CLK_PLLVDO_CRU2, 49 CLK_PLLVDO_CRU3, 50 51 /* Module Clocks */ 52 MOD_CLK_BASE, 53 }; 54 55 static const struct clk_div_table dtable_1_8[] = { 56 {0, 1}, 57 {1, 2}, 58 {2, 4}, 59 {3, 8}, 60 {0, 0}, 61 }; 62 63 static const struct clk_div_table dtable_2_4[] = { 64 {0, 2}, 65 {1, 4}, 66 {0, 0}, 67 }; 68 69 static const struct clk_div_table dtable_2_64[] = { 70 {0, 2}, 71 {1, 4}, 72 {2, 8}, 73 {3, 16}, 74 {4, 64}, 75 {0, 0}, 76 }; 77 78 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 79 /* External Clock Inputs */ 80 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 81 DEF_INPUT("rtxin", CLK_RTXIN), 82 DEF_INPUT("qextal", CLK_QEXTAL), 83 84 /* PLL Clocks */ 85 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 86 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 87 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 88 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), 89 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 90 91 /* Internal Core Clocks */ 92 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), 93 DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33, 94 CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), 95 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 96 97 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 98 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 99 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 100 101 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 102 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 103 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 104 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 105 DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64), 106 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4), 107 108 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 109 DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4), 110 DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), 111 DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), 112 113 /* Core Clocks */ 114 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 115 DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55, 116 CDDIV1_DIVCTL0, dtable_1_8), 117 DEF_DDIV("ca55_0_coreclk1", R9A09G057_CA55_0_CORE_CLK1, CLK_PLLCA55, 118 CDDIV1_DIVCTL1, dtable_1_8), 119 DEF_DDIV("ca55_0_coreclk2", R9A09G057_CA55_0_CORE_CLK2, CLK_PLLCA55, 120 CDDIV1_DIVCTL2, dtable_1_8), 121 DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55, 122 CDDIV1_DIVCTL3, dtable_1_8), 123 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 124 }; 125 126 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 127 DEF_MOD("dmac_0_aclk", CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0, 128 BUS_MSTOP(5, BIT(9))), 129 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1, 130 BUS_MSTOP(3, BIT(2))), 131 DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2, 132 BUS_MSTOP(3, BIT(3))), 133 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3, 134 BUS_MSTOP(10, BIT(11))), 135 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4, 136 BUS_MSTOP(10, BIT(12))), 137 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 138 BUS_MSTOP_NONE), 139 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 140 BUS_MSTOP(3, BIT(5))), 141 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, 142 BUS_MSTOP(5, BIT(10))), 143 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, 144 BUS_MSTOP(5, BIT(11))), 145 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, 146 BUS_MSTOP(2, BIT(13))), 147 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, 148 BUS_MSTOP(2, BIT(14))), 149 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, 150 BUS_MSTOP(11, BIT(13))), 151 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, 152 BUS_MSTOP(11, BIT(14))), 153 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, 154 BUS_MSTOP(11, BIT(15))), 155 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 156 BUS_MSTOP(12, BIT(0))), 157 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, 158 BUS_MSTOP(3, BIT(10))), 159 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, 160 BUS_MSTOP(3, BIT(10))), 161 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 162 BUS_MSTOP(1, BIT(0))), 163 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 164 BUS_MSTOP(1, BIT(0))), 165 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 166 BUS_MSTOP(5, BIT(12))), 167 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 168 BUS_MSTOP(5, BIT(12))), 169 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 170 BUS_MSTOP(5, BIT(13))), 171 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 172 BUS_MSTOP(5, BIT(13))), 173 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 174 BUS_MSTOP(3, BIT(14))), 175 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 176 BUS_MSTOP(3, BIT(13))), 177 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 178 BUS_MSTOP(1, BIT(1))), 179 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 180 BUS_MSTOP(1, BIT(2))), 181 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 182 BUS_MSTOP(1, BIT(3))), 183 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 184 BUS_MSTOP(1, BIT(4))), 185 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 186 BUS_MSTOP(1, BIT(5))), 187 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 188 BUS_MSTOP(1, BIT(6))), 189 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 190 BUS_MSTOP(1, BIT(7))), 191 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 192 BUS_MSTOP(1, BIT(8))), 193 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 194 BUS_MSTOP(8, BIT(2))), 195 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 196 BUS_MSTOP(8, BIT(2))), 197 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 198 BUS_MSTOP(8, BIT(2))), 199 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 200 BUS_MSTOP(8, BIT(2))), 201 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 202 BUS_MSTOP(8, BIT(3))), 203 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 204 BUS_MSTOP(8, BIT(3))), 205 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 206 BUS_MSTOP(8, BIT(3))), 207 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 208 BUS_MSTOP(8, BIT(3))), 209 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 210 BUS_MSTOP(8, BIT(4))), 211 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 212 BUS_MSTOP(8, BIT(4))), 213 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 214 BUS_MSTOP(8, BIT(4))), 215 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 216 BUS_MSTOP(8, BIT(4))), 217 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 218 BUS_MSTOP(9, BIT(4))), 219 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 220 BUS_MSTOP(9, BIT(4))), 221 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 222 BUS_MSTOP(9, BIT(4))), 223 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21, 224 BUS_MSTOP(9, BIT(5))), 225 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22, 226 BUS_MSTOP(9, BIT(5))), 227 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23, 228 BUS_MSTOP(9, BIT(5))), 229 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24, 230 BUS_MSTOP(9, BIT(6))), 231 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25, 232 BUS_MSTOP(9, BIT(6))), 233 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26, 234 BUS_MSTOP(9, BIT(6))), 235 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27, 236 BUS_MSTOP(9, BIT(7))), 237 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28, 238 BUS_MSTOP(9, BIT(7))), 239 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, 240 BUS_MSTOP(9, BIT(7))), 241 }; 242 243 static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 244 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 245 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */ 246 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */ 247 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */ 248 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */ 249 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */ 250 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 251 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 252 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 253 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 254 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ 255 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ 256 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */ 257 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */ 258 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 259 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 260 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 261 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ 262 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 263 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 264 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 265 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 266 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 267 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 268 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 269 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 270 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 271 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 272 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 273 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 274 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 275 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 276 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 277 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 278 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 279 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 280 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 281 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */ 282 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */ 283 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */ 284 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */ 285 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */ 286 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */ 287 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ 288 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ 289 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ 290 }; 291 292 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { 293 /* Core Clocks */ 294 .core_clks = r9a09g057_core_clks, 295 .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks), 296 .last_dt_core_clk = LAST_DT_CORE_CLK, 297 .num_total_core_clks = MOD_CLK_BASE, 298 299 /* Module Clocks */ 300 .mod_clks = r9a09g057_mod_clks, 301 .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks), 302 .num_hw_mod_clks = 25 * 16, 303 304 /* Resets */ 305 .resets = r9a09g057_resets, 306 .num_resets = ARRAY_SIZE(r9a09g057_resets), 307 308 .num_mstop_bits = 192, 309 }; 310