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Searched +full:0 +full:xe0000000 (Results 1 – 25 of 39) sorted by relevance

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/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h164 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
167 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
168 #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
169 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
177 #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
179 #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
183 #define XCHAL_ITLB_WAY0_SET 0
186 #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
189 #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
192 /* ITLB way set 0 (group of ways 0 thru 0): */
[all …]
/qemu/tests/qtest/libqos/
H A Dmalloc-pc.c27 alloc_init(s, flags, 1 << 20, MIN(ram_size, 0xE0000000), ALLOC_PAGE_SIZE); in pc_alloc_init()
H A Dpci-pc.c21 #define ACPI_PCIHP_ADDR 0xae00
22 #define PCI_EJ_BASE 0x0008
62 qtest_outl(bus->qts, addr, val & 0xffffffff); in qpci_pc_pio_writeq()
79 qtest_outl(bus->qts, 0xcf8, (1U << 31) | (devfn << 8) | offset); in qpci_pc_config_readb()
80 return qtest_inb(bus->qts, 0xcfc); in qpci_pc_config_readb()
85 qtest_outl(bus->qts, 0xcf8, (1U << 31) | (devfn << 8) | offset); in qpci_pc_config_readw()
86 return qtest_inw(bus->qts, 0xcfc); in qpci_pc_config_readw()
91 qtest_outl(bus->qts, 0xcf8, (1U << 31) | (devfn << 8) | offset); in qpci_pc_config_readl()
92 return qtest_inl(bus->qts, 0xcfc); in qpci_pc_config_readl()
97 qtest_outl(bus->qts, 0xcf8, (1U << 31) | (devfn << 8) | offset); in qpci_pc_config_writeb()
[all …]
/qemu/include/hw/display/
H A Dbochs-vbe.h12 #define VBE_DISPI_INDEX_ID 0x0
13 #define VBE_DISPI_INDEX_XRES 0x1
14 #define VBE_DISPI_INDEX_YRES 0x2
15 #define VBE_DISPI_INDEX_BPP 0x3
16 #define VBE_DISPI_INDEX_ENABLE 0x4
17 #define VBE_DISPI_INDEX_BANK 0x5
18 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
19 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
20 #define VBE_DISPI_INDEX_X_OFFSET 0x8
21 #define VBE_DISPI_INDEX_Y_OFFSET 0x9
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/qemu/include/hw/sh4/
H A Dsh.h33 #define A7ADDR(x) ((x) & 0x1fffffff)
34 #define P4ADDR(x) ((x) | 0xe0000000)
42 #define SH_SERIAL_FEAT_SCIF (1 << 0)
/qemu/tests/qtest/
H A Dfuzz-sdcard-test.c24 " -drive if=none,index=0,file=null-co://,format=raw,id=d0"); in oss_fuzz_29225()
26 qtest_outl(s, 0xcf8, 0x80001010); in oss_fuzz_29225()
27 qtest_outl(s, 0xcfc, 0xd0690); in oss_fuzz_29225()
28 qtest_outl(s, 0xcf8, 0x80001003); in oss_fuzz_29225()
29 qtest_outl(s, 0xcf8, 0x80001013); in oss_fuzz_29225()
30 qtest_outl(s, 0xcfc, 0xffffffff); in oss_fuzz_29225()
31 qtest_outl(s, 0xcf8, 0x80001003); in oss_fuzz_29225()
32 qtest_outl(s, 0xcfc, 0x3effe00); in oss_fuzz_29225()
34 qtest_bufwrite(s, 0xff0d062c, "\xff", 0x1); in oss_fuzz_29225()
35 qtest_bufwrite(s, 0xff0d060f, "\xb7", 0x1); in oss_fuzz_29225()
[all …]
/qemu/target/sh4/
H A Dhelper.c33 #define MMU_OK 0
53 return !(addr & 0x80000000); in cpu_sh4_is_cached()
70 if (do_exp && cs->exception_index != 0x1e0) { in superh_cpu_do_interrupt()
84 env->in_sleep = 0; in superh_cpu_do_interrupt()
88 (env->sr >> 4) & 0xf); in superh_cpu_do_interrupt()
97 case 0x0e0: in superh_cpu_do_interrupt()
100 case 0x040: in superh_cpu_do_interrupt()
103 case 0x0a0: in superh_cpu_do_interrupt()
106 case 0x180: in superh_cpu_do_interrupt()
109 case 0x1a0: in superh_cpu_do_interrupt()
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/qemu/hw/net/rocker/
H A Drocker.h31 } while (0)
35 return 0; in DPRINTF()
41 return (addr & htonl(0xf0000000)) == htonl(0xe0000000); in ipv4_addr_is_multicast()
54 return (addr->addr32[0] & htonl(0xFF000000)) == htonl(0xFF000000); in ipv6_addr_is_multicast()
/qemu/docs/specs/
H A Dstandard-vga.rst27 PCI Region 0
63 ``0xe0000000``
78 vga ioports (``0x3c0`` to ``0x3df``), remapped 1:1. Word access
93 - ``0xbebebebe`` indicates big endian.
94 - ``0x1e1e1e1e`` indicates little endian.
/qemu/docs/devel/
H A Dmemory.rst227 For example, suppose we have a container A of size 0x8000 with two subregions
228 B and C. B is a container mapped at 0x2000, size 0x4000, priority 2; C is
229 an MMIO region mapped at 0x0, size 0x6000, priority 1. B currently has two
230 of its own subregions: D of size 0x1000 at offset 0 and E of size 0x1000 at
231 offset 0x2000. As a diagram::
233 0 1000 2000 3000 4000 5000 6000 7000 8000
295 system_memory: container@0-2^48-1
297 +---- lomem: alias@0-0xdfffffff ---> #ram (0-0xdfffffff)
299 +---- himem: alias@0x100000000-0x11fffffff ---> #ram (0xe0000000-0xffffffff)
301 +---- vga-window: alias@0xa0000-0xbffff ---> #pci (0xa0000-0xbffff)
[all …]
/qemu/include/hw/i386/
H A Dmicrovm.h33 * 0 | pit |
37 * 4 | serial 0 | serial
47 * 14 | ide 0 | pcie
53 #define VIRTIO_MMIO_BASE 0xfeb00000
56 #define GED_MMIO_BASE 0xfea00000
57 #define GED_MMIO_BASE_MEMHP (GED_MMIO_BASE + 0x100)
58 #define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200)
61 #define MICROVM_XHCI_BASE 0xfe900000
64 #define PCIE_MMIO_BASE 0xc0000000
65 #define PCIE_MMIO_SIZE 0x20000000
[all …]
/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_dpaq_sa_l_w.c7 int ach = 0, acl = 0; in main()
10 rs = 0x80000000; in main()
11 rt = 0x80000000; in main()
12 resulth = 0x7FFFFFFF; in main()
13 resultl = 0xFFFFFFFF; in main()
14 resultdsp = 0x01; in main()
16 ("mthi %0, $ac1\n\t" in main()
19 "mfhi %0, $ac1\n\t" in main()
25 dsp = (dsp >> 17) & 0x01; in main()
30 ach = 0x00000012; in main()
[all …]
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h105 #define XCHAL_CA_R (0xC0 | 0x40000000)
106 #define XCHAL_CA_RX (0xD0 | 0x40000000)
107 #define XCHAL_CA_RW (0xE0 | 0x40000000)
108 #define XCHAL_CA_RWX (0xF0 | 0x40000000)
119 #define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
129 #define XCHAL_CA_BYPASS_R 0 /* cache disabled (bypassed) mode (no exec, no write) */
180 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
183 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
184 #define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
185 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
[all …]
/qemu/hw/arm/
H A Darmv7m.c34 return s->base | (offset & 0x1ffffff) >> 5; in bitband_addr()
107 "bitband", 0x02000000); in bitband_init()
126 0x20000000, 0x40000000
130 0x22000000, 0x42000000
141 attrs.secure = 0; in v7m_sysreg_ns_write()
161 attrs.secure = 0; in v7m_sysreg_ns_read()
169 *data = 0; in v7m_sysreg_ns_read()
188 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); in v7m_systick_write()
201 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); in v7m_systick_read()
220 qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n", in ppb_default_read()
[all …]
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
56 0x33b,
57 0x33b,
58 0x769,
59 0x76d
70 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
72 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
73 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
95 int is_mpcore = 0; in realview_init()
[all …]
H A Dxilinx_zynq.c57 #define MPCORE_PERIPHBASE 0xF8F00000
58 #define ZYNQ_BOARD_MIDR 0x413FC090
66 #define BOARD_SETUP_ADDR 0x100
68 #define SLCR_LOCK_OFFSET 0x004
69 #define SLCR_UNLOCK_OFFSET 0x008
70 #define SLCR_ARM_PLL_OFFSET 0x100
72 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
73 #define SLCR_XILINX_LOCK_KEY 0x767b
75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
[all …]
H A Dmps3r.c83 #define PERIPHBASE 0xf0000000
136 .base = 0x00000000,
137 .size = 0x00008000,
138 .mrindex = 0,
142 .base = 0x08000000,
143 .size = 0x00800000,
148 .base = 0x10000000,
149 .size = 0x00080000,
153 .base = 0x20000000,
158 .base = 0xee000000,
[all …]
/qemu/target/mips/
H A Dcpu.c73 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", in fpu_dump_state()
76 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { in fpu_dump_state()
87 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx in mips_cpu_dump_state()
88 " LO=0x" TARGET_FMT_lx " ds %04x " in mips_cpu_dump_state()
90 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], in mips_cpu_dump_state()
92 for (i = 0; i < 32; i++) { in mips_cpu_dump_state()
93 if ((i & 3) == 0) { in mips_cpu_dump_state()
103 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" in mips_cpu_dump_state()
106 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" in mips_cpu_dump_state()
109 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", in mips_cpu_dump_state()
[all …]
/qemu/hw/i386/
H A Dpc_piix.c75 static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
76 static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
96 for (i = 0; i < PIIX_NUM_PIRQS; i++) { in piix_intx_routing_notifier_xen()
98 const uint8_t v = route.mode == PCI_INTX_ENABLED ? route.irq : 0; in piix_intx_routing_notifier_xen()
120 uint64_t hole64_size = 0; in pc_init1()
126 * - Traditional split is 3.5G (lowmem = 0xe0000000). This is the in pc_init1()
130 * (lowmem = 0xc0000000). But only in case we have to split in in pc_init1()
158 pcms->max_ram_below_4g = 0xe0000000; /* default: 3.5G */ in pc_init1()
163 if (lowmem > 0xc0000000) { in pc_init1()
164 lowmem = 0xc0000000; in pc_init1()
[all …]
/qemu/hw/sparc/
H A Dsun4m_iommu.c43 #define IOMMU_CTRL (0x0000 >> 2)
44 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
45 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
46 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
47 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
48 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
49 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
50 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
51 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
52 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
[all …]
/qemu/target/xtensa/
H A Dcpu.h112 LBEG = 0,
171 #define PS_INTLEVEL 0xf
172 #define PS_INTLEVEL_SHIFT 0
174 #define PS_EXCM 0x10
175 #define PS_UM 0x20
177 #define PS_RING 0xc0
180 #define PS_OWB 0xf00
184 #define PS_CALLINC 0x30000
188 #define PS_WOE 0x40000
190 #define DEBUGCAUSE_IC 0x1
[all …]
H A Dmmu_helper.c42 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f
43 #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00
45 #define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000
47 #define XTENSA_MPU_ATTR_MASK 0x001fff00
49 #define XTENSA_MPU_PROBE_B 0x40000000
50 #define XTENSA_MPU_PROBE_V 0x80000000
52 #define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001
53 #define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002
54 #define XTENSA_MPU_SYSTEM_TYPE_C 0x0003
55 #define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003
[all …]
/qemu/hw/sh4/
H A Dsh7750_regs.h42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */
46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
62 #define SH7750_PTEH_ASID_S 0
65 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
[all …]
/qemu/net/
H A Dslirp.c62 if (buf_size > 0) { in get_str_sep()
66 buf[len] = '\0'; in get_str_sep()
69 return 0; in get_str_sep()
191 #if SLIRP_CHECK_VERSION(4,7,0)
198 #if SLIRP_CHECK_VERSION(4,7,0)
250 #if !SLIRP_CHECK_VERSION(4, 9, 0)
264 FD_CONNECT | FD_WRITE | FD_OOB) != 0) { in net_slirp_register_poll_sock()
273 if (WSAEventSelect(fd, NULL, 0) != 0) { in net_slirp_unregister_poll_sock()
288 #if SLIRP_CHECK_VERSION(4,7,0)
303 int ret = 0; in slirp_poll_to_gio()
[all …]
/qemu/linux-user/arm/nwfpe/
H A Dfpopcode.h27 |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
28 |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT
30 |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
31 |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
32 |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
54 P pre/post index bit: 0 = postindex, 1 = preindex
55 U up/down bit: 0 = stack grows down, 1 = stack grows up
57 L load/store bit: 0 = store, 1 = load
69 j dyadic/monadic bit: 0 = dyadic, 1 = monadic
78 | Single | 0 | 0 | x | 1 words |
[all …]

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