Lines Matching +full:0 +full:xe0000000
73 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", in fpu_dump_state()
76 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { in fpu_dump_state()
87 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx in mips_cpu_dump_state()
88 " LO=0x" TARGET_FMT_lx " ds %04x " in mips_cpu_dump_state()
90 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], in mips_cpu_dump_state()
92 for (i = 0; i < 32; i++) { in mips_cpu_dump_state()
93 if ((i & 3) == 0) { in mips_cpu_dump_state()
103 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" in mips_cpu_dump_state()
106 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" in mips_cpu_dump_state()
109 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", in mips_cpu_dump_state()
111 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", in mips_cpu_dump_state()
197 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); in mips_cpu_reset_hold()
222 env->current_tc = 0; in mips_cpu_reset_hold()
266 env->CP0_HWREna |= 0x0000000F; in mips_cpu_reset_hold()
294 env->CP0_Wired = 0; in mips_cpu_reset_hold()
295 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; in mips_cpu_reset_hold()
296 env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF); in mips_cpu_reset_hold()
298 env->CP0_CMGCRBase = 0x1fbf8000 >> 4; in mips_cpu_reset_hold()
301 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; in mips_cpu_reset_hold()
313 env->CP0_IntCtl = 0xe0000000; in mips_cpu_reset_hold()
317 for (i = 0; i < 7; i++) { in mips_cpu_reset_hold()
318 env->CP0_WatchLo[i] = 0; in mips_cpu_reset_hold()
321 env->CP0_WatchLo[7] = 0; in mips_cpu_reset_hold()
322 env->CP0_WatchHi[7] = 0; in mips_cpu_reset_hold()
325 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); in mips_cpu_reset_hold()
332 /* Only TC0 on VPE 0 starts as active. */ in mips_cpu_reset_hold()
333 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { in mips_cpu_reset_hold()
340 if (cs->cpu_index == 0) { in mips_cpu_reset_hold()
346 cs->halted = 0; in mips_cpu_reset_hold()
347 env->active_tc.CP0_TCHalt = 0; in mips_cpu_reset_hold()
348 env->tcs[0].CP0_TCHalt = 0; in mips_cpu_reset_hold()
349 /* With thread 0 active. */ in mips_cpu_reset_hold()
351 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); in mips_cpu_reset_hold()
359 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ in mips_cpu_reset_hold()
361 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ in mips_cpu_reset_hold()
363 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ in mips_cpu_reset_hold()
364 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | in mips_cpu_reset_hold()
366 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ in mips_cpu_reset_hold()
367 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | in mips_cpu_reset_hold()
369 /* USeg (seg4 0x40000000..0x7FFFFFFF) */ in mips_cpu_reset_hold()
372 /* USeg (seg5 0x00000000..0x3FFFFFFF) */ in mips_cpu_reset_hold()
373 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | in mips_cpu_reset_hold()
375 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ in mips_cpu_reset_hold()
380 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ in mips_cpu_reset_hold()
386 env->CP0_PWSize = 0x40; in mips_cpu_reset_hold()
392 env->CP0_PWField = 0x0C30C302; in mips_cpu_reset_hold()
394 /* GDI = 0 */ in mips_cpu_reset_hold()
395 /* UDI = 0 */ in mips_cpu_reset_hold()
396 /* MDI = 0 */ in mips_cpu_reset_hold()
397 /* PRI = 0 */ in mips_cpu_reset_hold()
399 env->CP0_PWField = 0x02; in mips_cpu_reset_hold()
480 env->exception_base = (int32_t)0xBFC00000; in mips_cpu_realizefn()
500 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); in mips_cpu_initfn()
573 .guest_default_memory_order = 0,
662 for (i = 0; i < mips_defs_number; i++) { in mips_cpu_register_types()
686 return (env->cpu_model->insn_flags & isa_mask) != 0; in cpu_supports_isa()
692 return (mcc->cpu_def->insn_flags & isa) != 0; in cpu_type_supports_isa()
698 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; in cpu_type_supports_cps_smp()