Lines Matching +full:0 +full:xe0000000
43 #define IOMMU_CTRL (0x0000 >> 2)
44 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
45 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
46 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
47 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
48 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
49 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
50 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
51 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
52 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
53 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
54 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
55 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
56 #define IOMMU_CTRL_MASK 0x0000001d
58 #define IOMMU_BASE (0x0004 >> 2)
59 #define IOMMU_BASE_MASK 0x07fffc00
61 #define IOMMU_TLBFLUSH (0x0014 >> 2)
62 #define IOMMU_TLBFLUSH_MASK 0xffffffff
64 #define IOMMU_PGFLUSH (0x0018 >> 2)
65 #define IOMMU_PGFLUSH_MASK 0xffffffff
67 #define IOMMU_AFSR (0x1000 >> 2)
68 #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
69 #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
71 #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
73 #define IOMMU_AFSR_BE 0x10000000 /* Write access received error
75 #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
76 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
77 #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
79 #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
80 #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
81 #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
82 #define IOMMU_AFSR_MASK 0xff0fffff
84 #define IOMMU_AFAR (0x1004 >> 2)
86 #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
87 #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
88 #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
89 #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
90 #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
91 #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
92 #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
93 #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
94 #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
95 #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
96 #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
97 #define IOMMU_AER_MASK 0x801f000f
99 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configuration per-slot */
100 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configuration per-slot */
101 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configuration per-slot */
102 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configuration per-slot */
103 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
105 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
106 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
107 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
110 #define IOMMU_SBCFG_MASK 0x00010003
112 #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
113 #define IOMMU_ARBEN_MASK 0x001f0000
114 #define IOMMU_MID 0x00000008
116 #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
117 #define IOMMU_MASK_ID_MASK 0x00ffffff
119 #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
120 #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
123 #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
124 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
126 #define IOPTE_WRITE 0x00000004 /* Writable */
127 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
128 #define IOPTE_WAZ 0x00000001 /* Write as zeros */
168 s->iostart = 0xffffffffff000000ULL; in iommu_mem_write()
171 s->iostart = 0xfffffffffe000000ULL; in iommu_mem_write()
174 s->iostart = 0xfffffffffc000000ULL; in iommu_mem_write()
177 s->iostart = 0xfffffffff8000000ULL; in iommu_mem_write()
180 s->iostart = 0xfffffffff0000000ULL; in iommu_mem_write()
183 s->iostart = 0xffffffffe0000000ULL; in iommu_mem_write()
186 s->iostart = 0xffffffffc0000000ULL; in iommu_mem_write()
190 s->iostart = 0xffffffff80000000ULL; in iommu_mem_write()
294 int is_write = (flags & IOMMU_WO) ? 1 : 0; in sun4m_translate_iommu()
298 .iova = 0, in sun4m_translate_iommu()
299 .translated_addr = 0, in sun4m_translate_iommu()
300 .addr_mask = ~(hwaddr)0, in sun4m_translate_iommu()
345 memset(s->regs, 0, IOMMU_NREGS * 4); in iommu_reset()
346 s->iostart = 0; in iommu_reset()
372 DEFINE_PROP_UINT32("version", IOMMUState, version, 0),