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/linux-5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt8516.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
Dpinctrl-mt8167.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
/linux-5.10/arch/mips/boot/dts/netlogic/
Dxlp_evp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
Dxlp_svp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
Dxlp_fvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x37100 0x20>;
54 #size-cells = <0>;
55 reg = <0 0x37120 0x20>;
64 reg = <0x68>;
69 reg = <0x4c>;
[all …]
Dxlp_rvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
[all …]
Dxlp_gvp.dts17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
[all …]
/linux-5.10/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_reg.h11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
14 /* 3. RF register 0x00-2E */
19 /* 3. Page8(0x800) */
20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
23 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
24 #define rFPGA0_XA_HSSIParameter2 0x824
25 #define rFPGA0_XB_HSSIParameter1 0x828
26 #define rFPGA0_XB_HSSIParameter2 0x82c
[all …]
Dphydm_regdefine11n.h18 #define ODM_REG_TX_ANT_CTRL_11N 0x80C
19 #define ODM_REG_RX_DEFAULT_A_11N 0x858
20 #define ODM_REG_ANTSEL_CTRL_11N 0x860
21 #define ODM_REG_RX_ANT_CTRL_11N 0x864
22 #define ODM_REG_PIN_CTRL_11N 0x870
23 #define ODM_REG_SC_CNT_11N 0x8C4
25 #define ODM_REG_ANT_MAPPING1_11N 0x914
27 #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
28 #define ODM_REG_CCK_CCA_11N 0xA0A
29 #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
[all …]
/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-exynos.h20 #define EXYNOS_GPIO_ECON_OFFSET 0x700
21 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
22 #define EXYNOS_GPIO_EMASK_OFFSET 0x900
23 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00
24 #define EXYNOS_WKUP_ECON_OFFSET 0xE00
25 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
26 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
27 #define EXYNOS7_WKUP_ECON_OFFSET 0x700
28 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
29 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
[all …]
/linux-5.10/drivers/pinctrl/sirf/
Dpinctrl-atlas7.c30 #define N 0
33 #define BANK_DS 0
36 #define CLR_REG(r) ((r) + 0x04)
39 #define FUNC_CLEAR_MASK 0x7
40 #define FUNC_GPIO 0
41 #define FUNC_ANALOGUE 0x8
42 #define ANA_CLEAR_MASK 0x1
46 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
60 #define DS0 BIT(0)
61 #define DSZ 0
[all …]
/linux-5.10/arch/openrisc/mm/
Dinit.c47 unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 }; in zone_sizes_init()
110 for (j = 0; p < e && j < PTRS_PER_PTE; in map_ram()
124 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__, in map_ram()
140 for (i = 0; i < PTRS_PER_PGD; i++) in paging_init()
141 swapper_pg_dir[i] = __pgd(0); in paging_init()
165 unsigned long *dtlb_vector = __va(0x900); in paging_init()
166 unsigned long *itlb_vector = __va(0xa00); in paging_init()
189 mtspr(SPR_ICBIR, 0x900); in paging_init()
190 mtspr(SPR_ICBIR, 0xa00); in paging_init()
210 memset((void *)empty_zero_page, 0, PAGE_SIZE); in mem_init()
/linux-5.10/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/linux-5.10/drivers/bus/
Domap_l3_noc.h24 #define CUSTOM_ERROR 0x2
25 #define STANDARD_ERROR 0x0
26 #define INBAND_ERROR 0x0
27 #define L3_APPLICATION_ERROR 0x0
28 #define L3_DEBUG_ERROR 0x1
31 #define L3_TARG_STDERRLOG_MAIN 0x48
32 #define L3_TARG_STDERRLOG_HDR 0x4c
33 #define L3_TARG_STDERRLOG_MSTADDR 0x50
34 #define L3_TARG_STDERRLOG_INFO 0x58
35 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux-5.10/Documentation/devicetree/bindings/power/supply/
Dsc27xx-fg.txt28 ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
34 <3680000 10>, <3605000 5>, <3400000 0>;
38 sc2731_pmic: pmic@0 {
40 reg = <0>;
46 #size-cells = <0>;
50 reg = <0xa00>;
/linux-5.10/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h37 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
39 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
40 * 3. RF register 0x00-2E
45 * 1. Page1(0x100)
47 #define rPMAC_Reset 0x100
48 #define rPMAC_TxStart 0x104
49 #define rPMAC_TxLegacySIG 0x108
50 #define rPMAC_TxHTSIG1 0x10c
51 #define rPMAC_TxHTSIG2 0x110
52 #define rPMAC_PHYDebug 0x114
[all …]
/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dpmc.txt61 reg = <0xb00 0x100 0xa00 0x100>;
/linux-5.10/arch/mips/pistachio/
Dinit.c28 * Bits 7 to 0: Maintenance rev
30 #define PISTACHIO_CORE_REV_REG 0xB81483D0
31 #define PISTACHIO_CORE_REV_A1 0x00100006
32 #define PISTACHIO_CORE_REV_B0 0x00100106
70 #define DEFAULT_CPC_BASE_ADDR 0x1bde0000
71 #define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
89 (void *)(CAC_BASE + 0xa80) : in mips_nmi_setup()
90 (void *)(CAC_BASE + 0x380); in mips_nmi_setup()
91 memcpy(base, except_vec_nmi, 0x80); in mips_nmi_setup()
93 (unsigned long)base + 0x80); in mips_nmi_setup()
[all …]
/linux-5.10/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
55 #define rPMAC_TxStart 0x104
56 #define rPMAC_TxLegacySIG 0x108
57 #define rPMAC_TxHTSIG1 0x10c
58 #define rPMAC_TxHTSIG2 0x110
59 #define rPMAC_PHYDebug 0x114
[all …]
/linux-5.10/drivers/crypto/qat/qat_common/
Dicp_qat_hal.h8 MISC_CONTROL = 0x04,
9 ICP_RESET = 0x0c,
10 ICP_GLOBAL_CLK_ENABLE = 0x50
14 USTORE_ADDRESS = 0x000,
15 USTORE_DATA_LOWER = 0x004,
16 USTORE_DATA_UPPER = 0x008,
17 ALU_OUT = 0x010,
18 CTX_ARB_CNTL = 0x014,
19 CTX_ENABLES = 0x018,
20 CC_ENABLE = 0x01c,
[all …]
/linux-5.10/arch/powerpc/include/asm/
Dkvm_asm.h27 #define BOOKE_INTERRUPT_CRITICAL 0
69 #define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100
70 #define BOOK3S_INTERRUPT_MACHINE_CHECK 0x200
71 #define BOOK3S_INTERRUPT_DATA_STORAGE 0x300
72 #define BOOK3S_INTERRUPT_DATA_SEGMENT 0x380
73 #define BOOK3S_INTERRUPT_INST_STORAGE 0x400
74 #define BOOK3S_INTERRUPT_INST_SEGMENT 0x480
75 #define BOOK3S_INTERRUPT_EXTERNAL 0x500
76 #define BOOK3S_INTERRUPT_EXTERNAL_HV 0x502
77 #define BOOK3S_INTERRUPT_ALIGNMENT 0x600
[all …]
/linux-5.10/drivers/staging/rtl8192u/
Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
/linux-5.10/arch/arm/mach-s3c/
Dregs-syscon-power-s3c64xx.h14 #define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
28 #define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
30 #define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
31 #define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
32 #define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
33 #define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
35 #define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
37 #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
38 #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
39 #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
[all …]
/linux-5.10/include/dt-bindings/pinctrl/
Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/linux-5.10/arch/m68k/include/asm/
Dm54xxsim.h15 #define IOMEMSIZE 0x01000000
24 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
26 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
27 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
28 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
29 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
30 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
31 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
32 #define MCFINTC_IRLR 0x18 /* */
33 #define MCFINTC_IACKL 0x19 /* */
[all …]

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