Searched +full:0 +full:x7000f400 (Results 1 – 4 of 4) sorted by relevance
16 #define TEGRA_IRAM_BASE 0x4000000019 #define TEGRA_ARM_PERIF_BASE 0x5004000022 #define TEGRA_ARM_INT_DIST_BASE 0x5004100025 #define TEGRA_TMR1_BASE 0x6000500028 #define TEGRA_TMR2_BASE 0x6000500831 #define TEGRA_TMRUS_BASE 0x6000501034 #define TEGRA_TMR3_BASE 0x6000505037 #define TEGRA_TMR4_BASE 0x6000505840 #define TEGRA_CLK_RESET_BASE 0x6000600043 #define TEGRA_FLOW_CTRL_BASE 0x60007000[all …]
40 "^emc-timings-[0-9]+$":49 "^timing-[0-9]+$":62 minimum: 078 Mode Register 0.85 minimum: 0224 reg = <0x7000f400 0x400>;225 interrupts = <0 78 4>;236 nvidia,emc-auto-cal-interval = <0x001fffff>;237 nvidia,emc-mode-1 = <0x80100002>;238 nvidia,emc-mode-2 = <0x80200018>;[all …]
15 memory@0 {17 reg = <0 0>;22 reg = <0x40000000 0x40000>;25 ranges = <0 0x40000000 0x40000>;28 reg = <0x400 0x3fc00>;35 reg = <0x50000000 0x00024000>;47 ranges = <0x54000000 0x54000000 0x04000000>;51 reg = <0x54040000 0x00040000>;60 reg = <0x54080000 0x00040000>;69 reg = <0x540c0000 0x00040000>;[all …]
17 reg = <0x80000000 0x0>;23 reg = <0x00003000 0x00000800>, /* PADS registers */24 <0x00003800 0x00000200>, /* AFI registers */25 <0x10000000 0x10000000>; /* configuration space */32 interrupt-map-mask = <0 0 0 0>;33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;35 bus-range = <0x00 0xff>;39 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */40 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */41 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */[all …]