Lines Matching +full:0 +full:x7000f400
17 reg = <0x80000000 0x0>;
23 reg = <0x00003000 0x00000800>, /* PADS registers */
24 <0x00003800 0x00000200>, /* AFI registers */
25 <0x10000000 0x10000000>; /* configuration space */
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35 bus-range = <0x00 0xff>;
39 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
40 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
41 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
42 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
43 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
44 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
57 pci@1,0 {
59 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
61 bus-range = <0x00 0xff>;
71 pci@2,0 {
73 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
74 reg = <0x001000 0 0 0 0>;
75 bus-range = <0x00 0xff>;
85 pci@3,0 {
87 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
88 reg = <0x001800 0 0 0 0>;
89 bus-range = <0x00 0xff>;
102 reg = <0x40000000 0x40000>;
105 ranges = <0 0x40000000 0x40000>;
108 reg = <0x400 0x3fc00>;
115 reg = <0x50000000 0x00024000>;
128 ranges = <0x54000000 0x54000000 0x04000000>;
132 reg = <0x54040000 0x00040000>;
143 reg = <0x54080000 0x00040000>;
154 reg = <0x540c0000 0x00040000>;
165 reg = <0x54100000 0x00040000>;
176 reg = <0x54140000 0x00040000>;
187 reg = <0x54180000 0x00040000>;
201 reg = <0x54200000 0x00040000>;
211 nvidia,head = <0>;
220 reg = <0x54240000 0x00040000>;
239 reg = <0x54280000 0x00040000>;
251 reg = <0x542c0000 0x00040000>;
259 reg = <0x54300000 0x00040000>;
270 reg = <0x54400000 0x00040000>;
282 reg = <0x50040600 0x20>;
291 reg = <0x50041000 0x1000>,
292 <0x50040100 0x0100>;
300 reg = <0x50043000 0x1000>;
309 reg = <0x60004000 0x100>,
310 <0x60004100 0x50>,
311 <0x60004200 0x50>,
312 <0x60004300 0x50>,
313 <0x60004400 0x50>;
321 reg = <0x60005000 0x400>;
322 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
333 reg = <0x60006000 0x1000>;
340 reg = <0x60007000 0x1000>;
345 reg = <0x6000a000 0x1400>;
386 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
391 reg = <0x6000c800 0x400>;
402 reg = <0x6000d000 0x1000>;
416 gpio-ranges = <&pinmux 0 0 248>;
422 reg = <0x6001a000 0x1000>, /* Syntax Engine */
423 <0x6001b000 0x1000>, /* Video Bitstream Engine */
424 <0x6001c000 0x100>, /* Macroblock Engine */
425 <0x6001c200 0x100>, /* Post-processing Engine */
426 <0x6001c400 0x100>, /* Motion Compensation Engine */
427 <0x6001c600 0x100>, /* Transform Engine */
428 <0x6001c800 0x100>, /* Pixel prediction block */
429 <0x6001ca00 0x100>, /* Video DMA */
430 <0x6001d800 0x400>; /* Video frame controls */
446 reg = <0x70000800 0x64>, /* Chip revision */
447 <0x70000008 0x04>; /* Strapping options */
452 reg = <0x70000868 0x0d4>, /* Pad control registers */
453 <0x70003000 0x3e4>; /* Mux registers */
466 reg = <0x70006000 0x40>;
479 reg = <0x70006040 0x40>;
492 reg = <0x70006200 0x100>;
505 reg = <0x70006300 0x100>;
518 reg = <0x70006400 0x100>;
531 reg = <0x70009000 0x1000>;
534 ranges = <0 0 0x48000000 0x7ffffff>;
544 reg = <0x7000a000 0x100>;
554 reg = <0x7000e000 0x100>;
561 reg = <0x7000c000 0x100>;
564 #size-cells = <0>;
577 reg = <0x7000c400 0x100>;
580 #size-cells = <0>;
593 reg = <0x7000c500 0x100>;
596 #size-cells = <0>;
609 reg = <0x7000c700 0x100>;
612 #size-cells = <0>;
625 reg = <0x7000d000 0x100>;
628 #size-cells = <0>;
641 reg = <0x7000d400 0x200>;
644 #size-cells = <0>;
655 reg = <0x7000d600 0x200>;
658 #size-cells = <0>;
669 reg = <0x7000d800 0x200>;
672 #size-cells = <0>;
683 reg = <0x7000da00 0x200>;
686 #size-cells = <0>;
697 reg = <0x7000dc00 0x200>;
700 #size-cells = <0>;
711 reg = <0x7000de00 0x200>;
714 #size-cells = <0>;
725 reg = <0x7000e200 0x100>;
735 reg = <0x7000e400 0x400>;
743 reg = <0x7000f000 0x400>;
755 reg = <0x7000f400 0x400>;
764 reg = <0x7000f800 0x400>;
773 reg = <0x70030000 0x10000>;
788 reg = <0x70080000 0x200>,
789 <0x70080200 0x100>;
820 reg = <0x70080300 0x100>;
830 reg = <0x70080400 0x100>;
840 reg = <0x70080500 0x100>;
850 reg = <0x70080600 0x100>;
860 reg = <0x70080700 0x100>;
871 reg = <0x78000000 0x200>;
882 reg = <0x78000200 0x200>;
893 reg = <0x78000400 0x200>;
904 reg = <0x78000600 0x200>;
915 reg = <0x7d000000 0x4000>;
928 reg = <0x7d000000 0x4000>,
929 <0x7d000000 0x4000>;
937 #phy-cells = <0>;
955 reg = <0x7d004000 0x4000>;
967 reg = <0x7d004000 0x4000>,
968 <0x7d000000 0x4000>;
976 #phy-cells = <0>;
993 reg = <0x7d008000 0x4000>;
1005 reg = <0x7d008000 0x4000>,
1006 <0x7d000000 0x4000>;
1014 #phy-cells = <0>;
1015 nvidia,hssync-start-delay = <0>;
1031 #size-cells = <0>;
1033 cpu@0 {
1036 reg = <0>;
1068 interrupt-affinity = <&{/cpus/cpu@0}>,