Lines Matching +full:0 +full:x7000f400
15 memory@0 {
17 reg = <0 0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00024000>;
47 ranges = <0x54000000 0x54000000 0x04000000>;
51 reg = <0x54040000 0x00040000>;
60 reg = <0x54080000 0x00040000>;
69 reg = <0x540c0000 0x00040000>;
78 reg = <0x54100000 0x00040000>;
87 reg = <0x54140000 0x00040000>;
96 reg = <0x54180000 0x00040000>;
104 reg = <0x54200000 0x00040000>;
112 nvidia,head = <0>;
121 reg = <0x54240000 0x00040000>;
138 reg = <0x54280000 0x00040000>;
150 reg = <0x542c0000 0x00040000>;
158 reg = <0x54300000 0x00040000>;
171 reg = <0x50040600 0x20>;
179 reg = <0x50041000 0x1000>,
180 <0x50040100 0x0100>;
188 reg = <0x50043000 0x1000>;
197 reg = <0x60004000 0x100>,
198 <0x60004100 0x50>,
199 <0x60004200 0x50>,
200 <0x60004300 0x50>;
208 reg = <0x60005000 0x60>;
209 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
218 reg = <0x60006000 0x1000>;
225 reg = <0x60007000 0x1000>;
230 reg = <0x6000a000 0x1200>;
255 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
260 reg = <0x6000d000 0x1000>;
273 gpio-ranges = <&pinmux 0 0 224>;
279 reg = <0x6001a000 0x1000>, /* Syntax Engine */
280 <0x6001b000 0x1000>, /* Video Bitstream Engine */
281 <0x6001c000 0x100>, /* Macroblock Engine */
282 <0x6001c200 0x100>, /* Post-processing Engine */
283 <0x6001c400 0x100>, /* Motion Compensation Engine */
284 <0x6001c600 0x100>, /* Transform Engine */
285 <0x6001c800 0x100>, /* Pixel prediction block */
286 <0x6001ca00 0x100>, /* Video DMA */
287 <0x6001d800 0x300>; /* Video frame controls */
302 reg = <0x70000800 0x64>, /* Chip revision */
303 <0x70000008 0x04>; /* Strapping options */
308 reg = <0x70000014 0x10>, /* Tri-state registers */
309 <0x70000080 0x20>, /* Mux registers */
310 <0x700000a0 0x14>, /* Pull-up/down registers */
311 <0x70000868 0xa8>; /* Pad control registers */
316 reg = <0x70000c00 0x80>;
321 reg = <0x70002000 0x200>;
333 reg = <0x70002800 0x200>;
345 reg = <0x70002a00 0x200>;
364 reg = <0x70006000 0x40>;
377 reg = <0x70006040 0x40>;
390 reg = <0x70006200 0x100>;
403 reg = <0x70006300 0x100>;
416 reg = <0x70006400 0x100>;
429 reg = <0x70008000 0x100>;
431 #size-cells = <0>;
444 reg = <0x70009000 0x1000>;
447 ranges = <0 0 0xd0000000 0xfffffff>;
457 reg = <0x7000a000 0x100>;
467 reg = <0x7000e000 0x100>;
474 reg = <0x7000c000 0x100>;
477 #size-cells = <0>;
490 reg = <0x7000c380 0x80>;
493 #size-cells = <0>;
504 reg = <0x7000c400 0x100>;
507 #size-cells = <0>;
520 reg = <0x7000c500 0x100>;
523 #size-cells = <0>;
536 reg = <0x7000d000 0x200>;
539 #size-cells = <0>;
552 reg = <0x7000d400 0x200>;
555 #size-cells = <0>;
566 reg = <0x7000d600 0x200>;
569 #size-cells = <0>;
580 reg = <0x7000d800 0x200>;
583 #size-cells = <0>;
594 reg = <0x7000da00 0x200>;
597 #size-cells = <0>;
608 reg = <0x7000e200 0x100>;
618 reg = <0x7000e400 0x400>;
626 reg = <0x7000f000 0x00000400>, /* controller registers */
627 <0x58000000 0x02000000>; /* GART aperture */
632 #iommu-cells = <0>;
637 reg = <0x7000f400 0x200>;
641 #size-cells = <0>;
646 reg = <0x7000f800 0x400>;
656 reg = <0x80003000 0x00000800>, /* PADS registers */
657 <0x80003800 0x00000200>, /* AFI registers */
658 <0x90000000 0x10000000>; /* configuration space */
665 interrupt-map-mask = <0 0 0 0>;
666 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
668 bus-range = <0x00 0xff>;
672 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
673 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
674 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
675 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
676 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
688 pci@1,0 {
690 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
691 reg = <0x000800 0 0 0 0>;
692 bus-range = <0x00 0xff>;
702 pci@2,0 {
704 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
705 reg = <0x001000 0 0 0 0>;
706 bus-range = <0x00 0xff>;
719 reg = <0xc5000000 0x4000>;
733 reg = <0xc5000000 0x4000>,
734 <0xc5000000 0x4000>;
743 #phy-cells = <0>;
758 reg = <0xc5004000 0x4000>;
770 reg = <0xc5004000 0x4000>;
778 #phy-cells = <0>;
784 reg = <0xc5008000 0x4000>;
796 reg = <0xc5008000 0x4000>,
797 <0xc5000000 0x4000>;
806 #phy-cells = <0>;
819 reg = <0xc8000000 0x200>;
830 reg = <0xc8000200 0x200>;
841 reg = <0xc8000400 0x200>;
852 reg = <0xc8000600 0x200>;
863 #size-cells = <0>;
865 cpu@0 {
868 reg = <0>;
884 interrupt-affinity = <&{/cpus/cpu@0}>,