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/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h164 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
167 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
168 #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
169 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
177 #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
179 #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
183 #define XCHAL_ITLB_WAY0_SET 0
186 #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
189 #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
192 /* ITLB way set 0 (group of ways 0 thru 0): */
[all …]
/qemu/hw/arm/
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
56 0x33b,
57 0x33b,
58 0x769,
59 0x76d
70 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
72 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
73 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
95 int is_mpcore = 0; in realview_init()
[all …]
H A Dmsf2-soc.c35 #define MSF2_TIMER_BASE 0x40004000
36 #define MSF2_SYSREG_BASE 0x40038000
37 #define MSF2_EMAC_BASE 0x40041000
39 #define ENVM_BASE_ADDRESS 0x60000000
41 #define SRAM_BASE_ADDRESS 0x20000000
54 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
55 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
72 for (i = 0; i < MSF2_NUM_SPIS; i++) { in m2sxxx_soc_initfn()
78 s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0); in m2sxxx_soc_initfn()
79 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0); in m2sxxx_soc_initfn()
[all …]
H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
56 /* Number of virtio transports to create (0..8; limited by
100 [VE_NORFLASHALIAS] = 0,
101 /* CS7: 0x10000000 .. 0x10020000 */
102 [VE_SYSREGS] = 0x10000000,
103 [VE_SP810] = 0x10001000,
104 [VE_SERIALPCI] = 0x10002000,
105 [VE_PL041] = 0x10004000,
106 [VE_MMCI] = 0x10005000,
107 [VE_KMI0] = 0x10006000,
[all …]
H A Dmps2.c130 memory_region_init_alias(mr, NULL, name, orig, 0, in make_ram_alias()
166 * 0x21000000 .. 0x21ffffff : PSRAM (16MB) in mps2_common_init()
168 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 in mps2_common_init()
169 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 in mps2_common_init()
170 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 in mps2_common_init()
171 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 in mps2_common_init()
173 * 0x01000000 .. 0x01003fff : block RAM (16K) in mps2_common_init()
174 * 0x01004000 .. 0x01007fff : mirror of above in mps2_common_init()
175 * 0x01008000 .. 0x0100bfff : mirror of above in mps2_common_init()
176 * 0x0100c000 .. 0x0100ffff : mirror of above in mps2_common_init()
[all …]
H A Dversatilepb.c32 #define VERSATILE_FLASH_ADDR 0x34000000
69 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
81 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
103 case 0: /* STATUS */ in vpb_sic_read()
115 "vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
116 return 0; in vpb_sic_read()
141 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
150 "vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
170 for (i = 0; i < 32; i++) { in vpb_sic_init()
175 "vpb-sic", 0x1000); in vpb_sic_init()
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H A Dmps2-tz.c134 uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
191 /* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
210 .name = "ssram-0",
211 .base = 0x00000000,
212 .size = 0x00400000,
213 .mpc = 0,
214 .mrindex = 0,
217 .base = 0x28000000,
218 .size = 0x00200000,
223 .base = 0x28200000,
[all …]
H A Dsbsa-ref.c115 [SBSA_FLASH] = { 0, 0x20000000 },
117 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
119 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
120 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
121 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
122 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 },
123 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
124 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
125 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
126 [SBSA_UART] = { 0x60000000, 0x00001000 },
[all …]
/qemu/include/libdecnumber/
H A DdecNumberLocal.h50 /* 1=little-endian, 0=big-endian */
52 #define DECLITEND 0
58 #define DECUSE64 1 /* 1=use int64s, 0=int32 & smaller only */
60 /* Conditional check flags -- set these to 0 for best performance */
61 #define DECCHECK 0 /* 1 to enable robust checking */
62 #define DECALLOC 0 /* 1 to enable memory accounting */
63 #define DECTRACE 0 /* 1 to trace certain internals, etc. */
92 #define DECNOINT 0 /* 1 to check no internal use of 'int' */
103 extern const uShort DPD2BIN[1024]; /* DPD -> 0-999 */
104 extern const uShort BIN2DPD[1000]; /* 0-999 -> DPD */
[all …]
/qemu/target/xtensa/
H A Doverlay_tool.h39 #define XCHAL_HAVE_DEPBITS 0
43 #define XCHAL_HAVE_DFP 0
47 #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0
63 #define XCHAL_HAVE_DIV32 0
67 #define XCHAL_UNALIGNED_LOAD_HW 0
71 #define XCHAL_HAVE_VECBASE 0
72 #define XCHAL_VECBASE_RESET_VADDR 0
89 #define XCHAL_LOOP_BUFFER_SIZE 0
93 #define XCHAL_HAVE_EXTERN_REGS 0
97 #define XCHAL_HAVE_MPU 0
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/qemu/include/hw/arm/
H A Dexynos4210.h38 #define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
39 #define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
40 #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */
42 #define EXYNOS4210_IROM_BASE_ADDR 0x00000000
43 #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */
44 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
45 #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */
47 #define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
48 #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */
52 #define EXYNOS4210_SMP_BOOT_SIZE 0x1000
[all …]
H A Dfsl-imx6ul.h97 FSL_IMX6UL_MMDC_ADDR = 0x80000000,
100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
116 FSL_IMX6UL_UART6_ADDR = 0x021FC000,
118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
120 FSL_IMX6UL_UART5_ADDR = 0x021F4000,
121 FSL_IMX6UL_UART4_ADDR = 0x021F0000,
[all …]
H A Dfsl-imx7.h102 FSL_IMX7_MMDC_ADDR = 0x80000000,
105 FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000,
108 FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000,
111 FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000,
115 FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
118 FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
119 FSL_IMX7_DMA_APBH_SIZE = 0x8000,
122 FSL_IMX7_GPV6_ADDR = 0x32600000,
123 FSL_IMX7_GPV5_ADDR = 0x32500000,
124 FSL_IMX7_GPV4_ADDR = 0x32400000,
[all …]
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h40 * configured, and a value of 0 otherwise. These macros are always defined.
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
60 #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
64 #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
68 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
70 #define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
71 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
72 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
[all …]
/qemu/hw/mips/
H A Djazz.c72 address_space_read(&address_space_memory, 0x90000071, in rtc_read()
80 uint8_t buf = val & 0xff; in rtc_write()
81 address_space_write(&address_space_memory, 0x90000071, in rtc_write()
98 return 0xff; in dma_dummy_read()
138 sysbus_mmio_map(sysbus, 0, 0x80001000); in mips_jazz_init_net()
139 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); in mips_jazz_init_net()
143 checksum = 0; in mips_jazz_init_net()
144 for (i = 0; i < 6; i++) { in mips_jazz_init_net()
147 if (checksum > 0xff) { in mips_jazz_init_net()
148 checksum = (checksum + 1) & 0xff; in mips_jazz_init_net()
[all …]
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h105 #define XCHAL_CA_R (0xC0 | 0x40000000)
106 #define XCHAL_CA_RX (0xD0 | 0x40000000)
107 #define XCHAL_CA_RW (0xE0 | 0x40000000)
108 #define XCHAL_CA_RWX (0xF0 | 0x40000000)
119 #define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
129 #define XCHAL_CA_BYPASS_R 0 /* cache disabled (bypassed) mode (no exec, no write) */
180 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
183 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
184 #define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
185 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
[all …]
/qemu/hw/tricore/
H A Dtc27x_soc.c32 [TC27XD_DSPR2] = { 0x50000000, 120 * KiB },
33 [TC27XD_DCACHE2] = { 0x5001E000, 8 * KiB },
34 [TC27XD_DTAG2] = { 0x500C0000, 0xC00 },
35 [TC27XD_PSPR2] = { 0x50100000, 32 * KiB },
36 [TC27XD_PCACHE2] = { 0x50108000, 16 * KiB },
37 [TC27XD_PTAG2] = { 0x501C0000, 0x1800 },
38 [TC27XD_DSPR1] = { 0x60000000, 120 * KiB },
39 [TC27XD_DCACHE1] = { 0x6001E000, 8 * KiB },
40 [TC27XD_DTAG1] = { 0x600C0000, 0xC00 },
41 [TC27XD_PSPR1] = { 0x60100000, 32 * KiB },
[all …]
/qemu/hw/pci-host/
H A Dsabre.c49 #define PBM_PCI_IMR_MASK 0x7fffffff
50 #define PBM_PCI_IMR_ENABLED 0x80000000
57 #define RESET_MASK 0xf8000000
58 #define RESET_WCMASK 0x98000000
59 #define RESET_WMASK 0x60000000
80 if (s->pci_irq_in == 0ULL) { in sabre_check_irqs()
83 for (i = 0; i < 32; i++) { in sabre_check_irqs()
104 qemu_set_irq(s->ivec_irqs[irq_num], 0); in sabre_clear_request()
127 case 0x30 ... 0x4f: /* DMA error registers */ in sabre_config_write()
130 case 0xc00 ... 0xc3f: /* PCI interrupt control */ in sabre_config_write()
[all …]
H A Dbonito.c28 * VT686B_FUN0's devfn = (5<<3)+0
66 #define BONITO_BOOT_BASE 0x1fc00000
67 #define BONITO_BOOT_SIZE 0x00100000
69 #define BONITO_FLASH_BASE 0x1c000000
70 #define BONITO_FLASH_SIZE 0x03000000
72 #define BONITO_SOCKET_BASE 0x1f800000
73 #define BONITO_SOCKET_SIZE 0x00400000
75 #define BONITO_REG_BASE 0x1fe00000
76 #define BONITO_REG_SIZE 0x00040000
78 #define BONITO_DEV_BASE 0x1ff00000
[all …]
/qemu/linux-user/arm/nwfpe/
H A Dfpopcode.h27 |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
28 |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|0|1| o f f s e t | CPDT
30 |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
31 |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
32 |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
54 P pre/post index bit: 0 = postindex, 1 = preindex
55 U up/down bit: 0 = stack grows down, 1 = stack grows up
57 L load/store bit: 0 = store, 1 = load
69 j dyadic/monadic bit: 0 = dyadic, 1 = monadic
78 | Single | 0 | 0 | x | 1 words |
[all …]
/qemu/hw/scsi/
H A Dmfi.h44 #define MFI_IMSG0 0x10 /* Inbound message 0 */
45 #define MFI_IMSG1 0x14 /* Inbound message 1 */
46 #define MFI_OMSG0 0x18 /* Outbound message 0 */
47 #define MFI_OMSG1 0x1c /* Outbound message 1 */
48 #define MFI_IDB 0x20 /* Inbound doorbell */
49 #define MFI_ISTS 0x24 /* Inbound interrupt status */
50 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
51 #define MFI_ODB 0x2c /* Outbound doorbell */
52 #define MFI_OSTS 0x30 /* Outbound interrupt status */
53 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
[all …]
/qemu/include/
H A Delf.h22 #define PT_NULL 0
29 #define PT_LOOS 0x60000000
30 #define PT_HIOS 0x6fffffff
31 #define PT_LOPROC 0x70000000
32 #define PT_HIPROC 0x7fffffff
34 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
35 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
37 #define PT_MIPS_REGINFO 0x70000000
38 #define PT_MIPS_RTPROC 0x70000001
39 #define PT_MIPS_OPTIONS 0x70000002
[all …]
/qemu/disas/
H A Dhppa.c50 #define PA_PAGESIZE 0x1000
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
[all …]
H A Dmicroblaze.c137 /* gen purpose regs go from 0 to 31 */
140 #define REG_PC_MASK 0x8000
141 #define REG_MSR_MASK 0x8001
142 #define REG_EAR_MASK 0x8003
143 #define REG_ESR_MASK 0x8005
144 #define REG_FSR_MASK 0x8007
145 #define REG_BTR_MASK 0x800b
146 #define REG_EDR_MASK 0x800d
147 #define REG_PVR_MASK 0xa000
149 #define REG_PID_MASK 0x9000
[all …]
/qemu/target/mips/tcg/system/
H A Dtlb_helper.c36 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); in r4k_mips_tlb_flush_extra()
61 tlb->EHINV = 0; in r4k_fill_tlb()
70 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; in r4k_fill_tlb()
71 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; in r4k_fill_tlb()
72 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; in r4k_fill_tlb()
75 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12; in r4k_fill_tlb()
76 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; in r4k_fill_tlb()
77 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; in r4k_fill_tlb()
78 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; in r4k_fill_tlb()
94 for (idx = 0; idx < env->tlb->nb_tlb; idx++) { in r4k_helper_tlbinv()
[all …]

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