Lines Matching +full:0 +full:x60000000
32 [TC27XD_DSPR2] = { 0x50000000, 120 * KiB },
33 [TC27XD_DCACHE2] = { 0x5001E000, 8 * KiB },
34 [TC27XD_DTAG2] = { 0x500C0000, 0xC00 },
35 [TC27XD_PSPR2] = { 0x50100000, 32 * KiB },
36 [TC27XD_PCACHE2] = { 0x50108000, 16 * KiB },
37 [TC27XD_PTAG2] = { 0x501C0000, 0x1800 },
38 [TC27XD_DSPR1] = { 0x60000000, 120 * KiB },
39 [TC27XD_DCACHE1] = { 0x6001E000, 8 * KiB },
40 [TC27XD_DTAG1] = { 0x600C0000, 0xC00 },
41 [TC27XD_PSPR1] = { 0x60100000, 32 * KiB },
42 [TC27XD_PCACHE1] = { 0x60108000, 16 * KiB },
43 [TC27XD_PTAG1] = { 0x601C0000, 0x1800 },
44 [TC27XD_DSPR0] = { 0x70000000, 112 * KiB },
45 [TC27XD_PSPR0] = { 0x70100000, 24 * KiB },
46 [TC27XD_PCACHE0] = { 0x70106000, 8 * KiB },
47 [TC27XD_PTAG0] = { 0x701C0000, 0xC00 },
48 [TC27XD_PFLASH0_C] = { 0x80000000, 2 * MiB },
49 [TC27XD_PFLASH1_C] = { 0x80200000, 2 * MiB },
50 [TC27XD_OLDA_C] = { 0x8FE70000, 32 * KiB },
51 [TC27XD_BROM_C] = { 0x8FFF8000, 32 * KiB },
52 [TC27XD_LMURAM_C] = { 0x90000000, 32 * KiB },
53 [TC27XD_EMEM_C] = { 0x9F000000, 1 * MiB },
54 [TC27XD_PFLASH0_U] = { 0xA0000000, 0x0 },
55 [TC27XD_PFLASH1_U] = { 0xA0200000, 0x0 },
56 [TC27XD_DFLASH0] = { 0xAF000000, 1 * MiB + 16 * KiB },
57 [TC27XD_DFLASH1] = { 0xAF110000, 64 * KiB },
58 [TC27XD_OLDA_U] = { 0xAFE70000, 0x0 },
59 [TC27XD_BROM_U] = { 0xAFFF8000, 0x0 },
60 [TC27XD_LMURAM_U] = { 0xB0000000, 0x0 },
61 [TC27XD_EMEM_U] = { 0xBF000000, 0x0 },
62 [TC27XD_PSPRX] = { 0xC0000000, 0x0 },
63 [TC27XD_DSPRX] = { 0xD0000000, 0x0 },
95 memory_region_init_alias(mr, NULL, name, orig, 0, in make_alias()