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/kvm-unit-tests/lib/x86/
H A Disr.c71 set_idt_entry(vec, thunk, 0); in handle_irq()
75 *thunk++ = 0x48; *thunk++ = 0x83; *thunk++ = 0xec; *thunk++ = 0x08; in handle_irq()
77 *thunk++ = 0xc7; *thunk++ = 0x04; *thunk++ = 0x24; in handle_irq()
80 *thunk++ = 0xc7; *thunk++ = 0x44; *thunk++ = 0x24; *thunk++ = 0x04; in handle_irq()
83 *thunk ++ = 0xe9; in handle_irq()
87 *thunk++ = 0x68; in handle_irq()
90 *thunk++ = 0xe9; in handle_irq()
108 "and $0xfffffffffffffff0, %%rsp\n\t" in handle_external_interrupt()
113 "orl $0x200, (%%"R "sp)\n\t" in handle_external_interrupt()
H A Ddesc.h6 * 0x00 NULL descriptor NULL descriptor
7 * 0x08 ring-0 code segment (32-bit) ring-0 code segment (64-bit)
8 * 0x10 ring-0 data segment (32-bit) ring-0 data segment (32/64-bit)
9 * 0x18 ring-0 code segment (P=0) ring-0 code segment (64-bit, P=0)
10 * 0x20 intr_alt_stack TSS ring-0 code segment (32-bit)
11 * 0x28 ring-0 code segment (16-bit) same
12 * 0x30 ring-0 data segment (16-bit) same
13 * 0x38 (0x3b) ring-3 code segment (32-bit) same
14 * 0x40 (0x43) ring-3 data segment (32-bit) ring-3 data segment (32/64-bit)
15 * 0x48 (0x4b) **unused** ring-3 code segment (64-bit)
[all …]
H A Ddesc.c11 idt_entry_t boot_idt[256] = {0};
21 { 0, 0, 0, .type_limit_flags = 0x0000}, /* 0x00 null */
22 {0xffff, 0, 0, .type_limit_flags = 0xcf9b}, /* flat 32-bit code segment */
23 {0xffff, 0, 0, .type_limit_flags = 0xcf93}, /* flat 32-bit data segment */
24 {0xffff, 0, 0, .type_limit_flags = 0xcf1b}, /* flat 32-bit code segment, not present */
25 { 0, 0, 0, .type_limit_flags = 0x0000}, /* TSS for task gates */
26 {0xffff, 0, 0, .type_limit_flags = 0x8f9b}, /* 16-bit code segment */
27 {0xffff, 0, 0, .type_limit_flags = 0x8f93}, /* 16-bit data segment */
28 {0xffff, 0, 0, .type_limit_flags = 0xcffb}, /* 32-bit code segment (user) */
29 {0xffff, 0, 0, .type_limit_flags = 0xcff3}, /* 32-bit data segment (user) */
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/kvm-unit-tests/x86/
H A Dcet.c12 static unsigned long invalid_offset = 0xffffffffffffff;
19 asm volatile (".byte 0xf3, 0x48, 0x0f, 0x1e, 0xc8" : "=a"(ssp)); in cet_shstk_func()
21 asm("movq %%rbp,%0" : "=r"(ret_addr)); in cet_shstk_func()
22 printf("The return-address in shadow-stack = 0x%lx, in normal stack = 0x%lx\n", in cet_shstk_func()
27 * while function is returning. The error-code is 0x1, meaning it's in cet_shstk_func()
32 *(ret_addr + 1) = 0xdeaddead; in cet_shstk_func()
34 return 0; in cet_shstk_func()
41 * endbr64, it'll trigger #CP with error code 0x3, and the execution in cet_ibt_func()
51 return 0; in cet_ibt_func()
54 #define ENABLE_SHSTK_BIT 0x1
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H A Dsvm.h111 #define TLB_CONTROL_DO_NOTHING 0
114 #define V_TPR_MASK 0x0f
126 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
154 #define SVM_VM_CR_VALID_MASK 0x001fULL
155 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
156 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
158 #define TSC_RATIO_DEFAULT 0x0100000000ULL
218 #define SVM_CPUID_FUNC 0x8000000a
230 #define SVM_SELECTOR_TYPE_MASK (0xf)
257 #define SVM_EVTINJ_VEC_MASK 0xff
[all …]
H A Dvmx.h21 } while (0)
27 } while (0)
38 } while (0)
53 char data[0];
191 VPID = 0x0000ul,
193 PINV = 0x0002ul,
195 EPTP_IDX = 0x0004ul,
198 GUEST_SEL_ES = 0x0800ul,
199 GUEST_SEL_CS = 0x0802ul,
200 GUEST_SEL_SS = 0x0804ul,
[all …]
/kvm-unit-tests/lib/s390x/
H A Dsclp-console.c27 0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F,
30 0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
32 0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26,
35 0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F,
37 0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D,
39 0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61,
40 /*30 0 1 2 3 4 5 6 7 */
41 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
43 0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F,
45 0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
[all …]
/kvm-unit-tests/lib/linux/
H A Dpci_regs.h30 #define PCI_VENDOR_ID 0x00 /* 16 bits */
31 #define PCI_DEVICE_ID 0x02 /* 16 bits */
32 #define PCI_COMMAND 0x04 /* 16 bits */
33 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
34 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
35 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
36 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
37 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
38 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
39 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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