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/qemu/hw/arm/
H A Dstm32f100_soc.c39 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
40 0x40004800 };
41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
53 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f100_soc_initfn()
58 for (i = 0; i < STM_NUM_SPIS; i++) { in stm32f100_soc_initfn()
62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn()
63 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f100_soc_initfn()
101 * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 in stm32f100_soc_realize()
106 "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE); in stm32f100_soc_realize()
108 memory_region_add_subregion(system_memory, 0, &s->flash_alias); in stm32f100_soc_realize()
[all …]
H A Dstm32f405_soc.c33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
[all …]
H A Dstm32l4x5_soc.c36 #define FLASH_BASE_ADDRESS 0x08000000
37 #define SRAM1_BASE_ADDRESS 0x20000000
39 #define SRAM2_BASE_ADDRESS 0x10000000
42 #define EXTI_ADDR 0x40010400
43 #define SYSCFG_ADDR 0x40010000
53 6, /* GPIO[0] */
81 #define RCC_BASE_ADDRESS 0x40021000
114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
[all …]
/qemu/tests/qemu-iotests/
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
H A D03325 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
74 do_test $align "write -P 0xa 0x200 0x400" "$TEST_IMG" | _filter_qemu_io
75 do_test $align "write -P 0xa 0x20000 0x600" "$TEST_IMG" | _filter_qemu_io
76 do_test $align "$write_zero_cmd 0x400 0x20000" "$TEST_IMG" | _filter_qemu_io
80 do_test $align "read -P 0xa 0x200 0x200" "$TEST_IMG" | _filter_qemu_io
81 do_test $align "read -P 0x0 0x400 0x20000" "$TEST_IMG" | _filter_qemu_io
82 do_test $align "read -P 0xa 0x20400 0x200" "$TEST_IMG" | _filter_qemu_io
86 do_test $align "write -P 0xb 0x10000 0x10000" "$TEST_IMG" | _filter_qemu_io
87 do_test $align "$write_zero_cmd 0x10000 0x10000" "$TEST_IMG" | _filter_qemu_io
[all …]
H A D241.out10 [{ "start": 0, "length": 1000, "depth": 0, "present": true, "zero": false, "data": true, "compresse…
11 { "start": 1000, "length": 24, "depth": 0, "present": true, "zero": true, "data": false, "compresse…
12 1 KiB (0x400) bytes allocated at offset 0 bytes (0x0)
21 [{ "start": 0, "length": 1024, "depth": 0, "present": true, "zero": false, "data": true, "compresse…
22 1 KiB (0x400) bytes allocated at offset 0 bytes (0x0)
24 …y detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
34 [{ "start": 0, "length": 1000, "depth": 0, "present": true, "zero": false, "data": true, "compresse…
35 { "start": 1000, "length": 24, "depth": 0, "present": true, "zero": true, "data": false, "compresse…
36 1 KiB (0x400) bytes allocated at offset 0 bytes (0x0)
H A D26326 seq=`basename $0`
35 trap "_cleanup; exit \$status" 0 1 2 3 15
58 …$QEMU_IO --object $SECRET -c "read -P 0 0 $size" --image-opts "$1" | _filter_qemu_io | _filter_tes…
62 …$QEMU_IO --object $SECRET -c "write -P 0xAA 0xFE00 0x400" --image-opts "$1" | _filter_qemu_io | _f…
66 …$QEMU_IO --object $SECRET -c "read -P 0x00 0x00000 0xFE00" --image-opts "$1" | _filter_qemu_io | _…
67 …$QEMU_IO --object $SECRET -c "read -P 0xAA 0x0FE00 0x400" --image-opts "$1" | _filter_qemu_io | _f…
68 …$QEMU_IO --object $SECRET -c "read -P 0x00 0x10200 0xEFE00" --image-opts "$1" | _filter_qemu_io | …
95 status=0
H A D28825 seq=`basename $0`
35 trap "_cleanup; exit \$status" 0 1 2 3 15
67 $QEMU_IO --object "$SECRET" --image-opts "$TEST_IMG" -c "write -P 0x51 0x10000 0x400" | _filter_qem…
84 QEMU_IO_OPTIONS= IMGOPTSSYNTAX= $QEMU_IO -f raw -c "write -P 0x51 0x10000 0x400" "$TEST_IMG_FILE" |…
94 status=0
/qemu/tests/tcg/i386/
H A Dtest-i386-fldcst.c11 int ret = 0; in main()
14 __asm__ volatile ("fnstcw %0" : "=m" (cw)); in main()
15 cw = (cw & ~0xc00) | 0x000; in main()
16 __asm__ volatile ("fldcw %0" : : "m" (cw)); in main()
18 if (ld_res != 0x3.5269e12f346e2bf8p+0L) { in main()
23 __asm__ volatile ("fnstcw %0" : "=m" (cw)); in main()
24 cw = (cw & ~0xc00) | 0x400; in main()
25 __asm__ volatile ("fldcw %0" : : "m" (cw)); in main()
27 if (ld_res != 0x3.5269e12f346e2bf8p+0L) { in main()
32 __asm__ volatile ("fnstcw %0" : "=m" (cw)); in main()
[all …]
/qemu/hw/intc/
H A Dpnv_xive_regs.h13 /* IC register offsets 0x0 - 0x400 */
14 #define CQ_SWI_CMD_HIST 0x020
15 #define CQ_SWI_CMD_POLL 0x028
16 #define CQ_SWI_CMD_BCAST 0x030
17 #define CQ_SWI_CMD_ASSIGN 0x038
18 #define CQ_SWI_CMD_BLK_UPD 0x040
19 #define CQ_SWI_RSP 0x048
20 #define CQ_CFG_PB_GEN 0x050
22 #define CQ_MSGSND 0x058
23 #define CQ_CNPM_SEL 0x078
[all …]
/qemu/hw/pci-host/
H A Dpnv_phb3_pbcq.c112 size = 0x1000; in pnv_pbcq_update_map()
137 pbcq->nest_regs[reg] = val & 0xffffffffc0000000ull; in pnv_pbcq_nest_xscom_write()
143 pbcq->nest_regs[reg] = val & 0xfffffffffc000000ull; in pnv_pbcq_nest_xscom_write()
146 pbcq->nest_regs[reg] = val & 0xf800000000000000ull; in pnv_pbcq_nest_xscom_write()
160 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_nest_xscom_write()
173 pbcq->pci_regs[reg] = val & 0xfffffffffc000000ull; in pnv_pbcq_pci_xscom_write()
177 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_pci_xscom_write()
190 pbcq->spci_regs[reg] = val & 0xfff; in pnv_pbcq_spci_xscom_write()
203 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_spci_xscom_write()
243 mm0 = 0x3d00000000000ull + 0x4000000000ull * phb->chip_id + in pnv_pbcq_default_bars()
[all …]
/qemu/hw/misc/
H A Dxlnx-zynqmp-crf.c20 #define XLNX_ZYNQMP_CRF_ERR_DEBUG 0
44 return 0; in ir_enable_prew()
54 return 0; in ir_disable_prew()
64 for (i = 0; i < CRF_MAX_CPU; i++) { in rst_fpd_apu_prew()
81 .w1c = 0x1,
84 .reset = 0x1,
85 .ro = 0x1,
92 .reset = 0x12c09,
93 .rsvd = 0xf88c80f6,
95 .rsvd = 0x1801210,
[all …]
/qemu/include/hw/s390x/
H A Ds390-pci-bus.h30 #define FH_MASK_ENABLE 0x80000000
31 #define FH_MASK_INSTANCE 0x7f000000
32 #define FH_MASK_SHM 0x00ff0000
33 #define FH_MASK_INDEX 0x0000ffff
34 #define FH_SHM_VFIO 0x00010000
35 #define FH_SHM_EMUL 0x00020000
36 #define ZPCI_MAX_FID 0xffffffff
37 #define ZPCI_MAX_UID 0xffff
38 #define UID_UNDEFINED 0
39 #define UID_CHECKING_ENABLED 0x01
[all …]
/qemu/tests/tcg/tricore/asm/
H A Dtest_ftohp.S5 TEST_D_D(ftohp, 1, 0xffff, 0xffffffff)
6 TEST_D_D(ftohp, 2, 0xfc00, 0xff800000)
7 TEST_D_D(ftohp, 3, 0x7c00, 0x7f800000)
8 TEST_D_D(ftohp, 4, 0x0, 0x0)
9 TEST_D_D(ftohp, 5, 0x5, 0x34a43580)
11 #TEST_D_D_PSW(ftohp, 6, 0x400, 0x8c000b80, 0x387fee74)
/qemu/tests/tcg/x86_64/
H A Dvsyscall.c4 #define VSYSCALL_PAGE 0xffffffffff600000
5 #define TIME_OFFSET 0x400
11 return 0; in main()
/qemu/include/hw/ppc/
H A Dpnv_xscom.h43 * GPIO 0x1100xxxx
44 * SCOM 0x1101xxxx
45 * OHA 0x1102xxxx
46 * CLOCK CTL 0x1103xxxx
47 * FIR 0x1104xxxx
48 * THERM 0x1105xxxx
49 * <reserved> 0x1106xxxx
51 * 0x110Exxxx
52 * PCB SLAVE 0x110Fxxxx
55 #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
[all …]
/qemu/linux-user/include/host/ppc/
H A Dhost-signal.h35 return uc->uc_mcontext.regs->trap != 0x400 in host_signal_write()
36 && (uc->uc_mcontext.regs->dsisr & 0x02000000); in host_signal_write()
/qemu/include/hw/pci-host/
H A Dls7a.h16 #define VIRT_PCI_MEM_BASE 0x40000000UL
17 #define VIRT_PCI_MEM_SIZE 0x40000000UL
18 #define VIRT_PCI_IO_OFFSET 0x4000
19 #define VIRT_PCI_CFG_BASE 0x20000000
20 #define VIRT_PCI_CFG_SIZE 0x08000000
21 #define VIRT_PCI_IO_BASE 0x18004000UL
22 #define VIRT_PCI_IO_SIZE 0xC000
24 #define VIRT_PCH_REG_BASE 0x10000000UL
26 #define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
27 #define VIRT_PCH_REG_SIZE 0x400
[all …]
/qemu/include/hw/nvram/
H A Dnrf51_nvm.h8 * + sysbus MMIO regions 0: NVMC peripheral registers
32 #define NRF51_NVMC_SIZE 0x1000
34 #define NRF51_NVMC_READY 0x400
35 #define NRF51_NVMC_READY_READY 0x01
36 #define NRF51_NVMC_CONFIG 0x504
37 #define NRF51_NVMC_CONFIG_MASK 0x03
38 #define NRF51_NVMC_CONFIG_WEN 0x01
39 #define NRF51_NVMC_CONFIG_EEN 0x02
40 #define NRF51_NVMC_ERASEPCR1 0x508
41 #define NRF51_NVMC_ERASEPCR0 0x510
[all …]
/qemu/linux-user/include/host/ppc64/
H A Dhost-signal.h37 return uc->uc_mcontext.gp_regs[PT_TRAP] != 0x400 in host_signal_write()
38 && (uc->uc_mcontext.gp_regs[PT_DSISR] & 0x02000000); in host_signal_write()
/qemu/include/hw/display/
H A Dbochs-vbe.h12 #define VBE_DISPI_INDEX_ID 0x0
13 #define VBE_DISPI_INDEX_XRES 0x1
14 #define VBE_DISPI_INDEX_YRES 0x2
15 #define VBE_DISPI_INDEX_BPP 0x3
16 #define VBE_DISPI_INDEX_ENABLE 0x4
17 #define VBE_DISPI_INDEX_BANK 0x5
18 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
19 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
20 #define VBE_DISPI_INDEX_X_OFFSET 0x8
21 #define VBE_DISPI_INDEX_Y_OFFSET 0x9
[all …]
/qemu/include/hw/timer/
H A Dhpet.h19 #define HPET_BASE 0xfed00000
20 #define HPET_LEN 0x400
29 #define HPET_LEGACY_PIT_INT 0
32 #define HPET_CFG_ENABLE 0x001
33 #define HPET_CFG_LEGACY 0x002
35 #define HPET_ID 0x000
36 #define HPET_PERIOD 0x004
37 #define HPET_CFG 0x010
38 #define HPET_STATUS 0x020
39 #define HPET_COUNTER 0x0f0
[all …]
/qemu/include/hw/audio/
H A Dasc.h22 ASC_TYPE_ASC = 0, /* original discrete Apple Sound Chip */
26 #define ASC_FIFO_OFFSET 0x0
27 #define ASC_FIFO_SIZE 0x400
29 #define ASC_REG_OFFSET 0x800
30 #define ASC_REG_SIZE 0x60
32 #define ASC_EXTREG_OFFSET 0xf00
33 #define ASC_EXTREG_SIZE 0x20
/qemu/include/hw/misc/
H A Daspeed_sdmc.h25 * - PHY status regs at offset 0x400, length 0x200
26 * - PHY setting regs at offset 0x100, length 0x300
33 #define ASPEED_SDMC_NR_REGS (0x1000 >> 2)
/qemu/ui/
H A Dkeymaps.h36 #define SCANCODE_KEYMASK 0xff
38 #define SCANCODE_KEYCODEMASK 0x7f
40 /* "grey" keys will usually need a 0xe0 prefix */
41 #define SCANCODE_GREY 0x80
42 #define SCANCODE_EMUL0 0xE0
43 #define SCANCODE_EMUL1 0xE1
45 #define SCANCODE_UP 0x80
48 #define SCANCODE_SHIFT 0x100
49 #define SCANCODE_CTRL 0x200
50 #define SCANCODE_ALT 0x400
[all …]

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