Lines Matching +full:0 +full:x400
112 size = 0x1000; in pnv_pbcq_update_map()
137 pbcq->nest_regs[reg] = val & 0xffffffffc0000000ull; in pnv_pbcq_nest_xscom_write()
143 pbcq->nest_regs[reg] = val & 0xfffffffffc000000ull; in pnv_pbcq_nest_xscom_write()
146 pbcq->nest_regs[reg] = val & 0xf800000000000000ull; in pnv_pbcq_nest_xscom_write()
160 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_nest_xscom_write()
173 pbcq->pci_regs[reg] = val & 0xfffffffffc000000ull; in pnv_pbcq_pci_xscom_write()
177 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_pci_xscom_write()
190 pbcq->spci_regs[reg] = val & 0xfff; in pnv_pbcq_spci_xscom_write()
203 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_spci_xscom_write()
243 mm0 = 0x3d00000000000ull + 0x4000000000ull * phb->chip_id + in pnv_pbcq_default_bars()
244 0x1000000000ull * phb->phb_id; in pnv_pbcq_default_bars()
245 mm1 = 0x3ff8000000000ull + 0x0200000000ull * phb->chip_id + in pnv_pbcq_default_bars()
246 0x0080000000ull * phb->phb_id; in pnv_pbcq_default_bars()
247 reg = 0x3fffe40000000ull + 0x0000400000ull * phb->chip_id + in pnv_pbcq_default_bars()
248 0x0000100000ull * phb->phb_id; in pnv_pbcq_default_bars()
253 pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0] = 0x3fff000000000ull << 14; in pnv_pbcq_default_bars()
254 pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1] = 0x3ffff80000000ull << 14; in pnv_pbcq_default_bars()
289 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, in pnv_pbcq_realize()
292 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, in pnv_pbcq_realize()
295 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, in pnv_pbcq_realize()
306 uint32_t lpc_pcba = PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id; in pnv_pbcq_dt_xscom()
310 cpu_to_be32(PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id), in pnv_pbcq_dt_xscom()
312 cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id), in pnv_pbcq_dt_xscom()
327 return 0; in pnv_pbcq_dt_xscom()