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/linux-6.15/Documentation/devicetree/bindings/display/
Dapple,h7-display-pipe-mipi.yaml36 port@0:
45 - port@0
59 reg = <0x28200000 0xc000>;
64 #size-cells = <0>;
66 port@0 {
67 reg = <0>;
Dapple,h7-display-pipe.yaml72 reg = <0x28200000 0xc000>,
73 <0x28400000 0x4000>;
80 iommus = <&displaydfr_dart 0>;
/linux-6.15/arch/arm64/boot/dts/mediatek/
Dmt7988a.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
21 reg = <0x0>;
32 reg = <0x1>;
43 reg = <0x2>;
54 reg = <0x3>;
63 cluster0_opp: opp-table-0 {
89 #clock-cells = <0>;
111 reg = <0 0x43000000 0 0x50000>;
124 reg = <0 0x0c000000 0 0x40000>, /* GICD */
[all …]
/linux-6.15/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux-6.15/arch/arm64/boot/dts/toshiba/
Dtmpv7708.dtsi14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
23 #size-cells = <0>;
57 cpu0: cpu@0 {
61 cpu-release-addr = <0x0 0x81100000>;
62 reg = <0x00>;
69 cpu-release-addr = <0x0 0x81100000>;
70 reg = <0x01>;
77 cpu-release-addr = <0x0 0x81100000>;
78 reg = <0x02>;
85 cpu-release-addr = <0x0 0x81100000>;
[all …]
/linux-6.15/arch/arm64/boot/dts/apple/
Dt8112.dtsi24 #size-cells = <0>;
58 cpu_e0: cpu@0 {
61 reg = <0x0 0x0>;
63 cpu-release-addr = <0 0>; /* To be filled by loader */
68 i-cache-size = <0x20000>;
69 d-cache-size = <0x10000>;
75 reg = <0x0 0x1>;
77 cpu-release-addr = <0 0>; /* To be filled by loader */
82 i-cache-size = <0x20000>;
83 d-cache-size = <0x10000>;
[all …]
Dt8103.dtsi23 #size-cells = <0>;
57 cpu_e0: cpu@0 {
60 reg = <0x0 0x0>;
62 cpu-release-addr = <0 0>; /* To be filled by loader */
67 i-cache-size = <0x20000>;
68 d-cache-size = <0x10000>;
74 reg = <0x0 0x1>;
76 cpu-release-addr = <0 0>; /* To be filled by loader */
81 i-cache-size = <0x20000>;
82 d-cache-size = <0x10000>;
[all …]
/linux-6.15/arch/arm64/boot/dts/qcom/
Dipq9574.dtsi26 #clock-cells = <0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
[all …]
/linux-6.15/arch/powerpc/include/asm/
Dppc-opcode.h13 #define __REG_R0 0
46 #define __REGA0_0 0
80 #define _R0 0
113 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
114 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
115 #define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
116 #define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
122 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
128 (((uintptr_t)(i) & 0x8000) >> 15))
133 #define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
[all …]
/linux-6.15/drivers/video/fbdev/
Di740fb.c120 #define REG_DDC_DRIVE 0x62
121 #define REG_DDC_STATE 0x63
130 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL); in i740fb_ddc_setscl()
138 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA); in i740fb_ddc_setsda()
145 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL); in i740fb_ddc_getscl()
154 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA); in i740fb_ddc_getsda()
189 return 0; in i740fb_open()
197 if (par->ref_count == 0) { in i740fb_release()
206 return 0; in i740fb_release()
224 wm = 0x18120000; in i740_calc_fifo()
[all …]
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/inc/
Dpolaris10_pwrvirus.h27 #define mmCP_HYP_MEC1_UCODE_ADDR 0xf81a
28 #define mmCP_HYP_MEC1_UCODE_DATA 0xf81b
29 #define mmCP_HYP_MEC2_UCODE_ADDR 0xf81c
30 #define mmCP_HYP_MEC2_UCODE_DATA 0xf81d
49 { 0x00000000, mmRLC_CNTL },
50 { 0x00000002, mmRLC_SRM_CNTL },
51 { 0x15000000, mmCP_ME_CNTL },
52 { 0x50000000, mmCP_MEC_CNTL },
53 { 0x80000004, mmCP_DFY_CNTL },
54 { 0x0840800a, mmCP_RB0_CNTL },
[all …]