Lines Matching +full:0 +full:x28200000
120 #define REG_DDC_DRIVE 0x62
121 #define REG_DDC_STATE 0x63
130 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL); in i740fb_ddc_setscl()
138 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA); in i740fb_ddc_setsda()
145 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL); in i740fb_ddc_getscl()
154 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA); in i740fb_ddc_getsda()
189 return 0; in i740fb_open()
197 if (par->ref_count == 0) { in i740fb_release()
206 return 0; in i740fb_release()
224 wm = 0x18120000; in i740_calc_fifo()
226 wm = 0x16110000; in i740_calc_fifo()
228 wm = 0x120E0000; in i740_calc_fifo()
230 wm = 0x100D0000; in i740_calc_fifo()
236 wm = 0x2C1D0000; in i740_calc_fifo()
238 wm = 0x2C180000; in i740_calc_fifo()
240 wm = 0x24160000; in i740_calc_fifo()
242 wm = 0x18120000; in i740_calc_fifo()
244 wm = 0x16110000; in i740_calc_fifo()
246 wm = 0x13100000; in i740_calc_fifo()
248 wm = 0x120E0000; in i740_calc_fifo()
251 wm = 0x28200000; in i740_calc_fifo()
253 wm = 0x2A1E0000; in i740_calc_fifo()
255 wm = 0x2B1A0000; in i740_calc_fifo()
257 wm = 0x2C180000; in i740_calc_fifo()
259 wm = 0x24180000; in i740_calc_fifo()
261 wm = 0x18120000; in i740_calc_fifo()
263 wm = 0x16110000; in i740_calc_fifo()
265 wm = 0x13100000; in i740_calc_fifo()
267 wm = 0x120E0000; in i740_calc_fifo()
273 wm = 0x31200000; in i740_calc_fifo()
275 wm = 0x2E200000; in i740_calc_fifo()
277 wm = 0x2C1D0000; in i740_calc_fifo()
279 wm = 0x25180000; in i740_calc_fifo()
281 wm = 0x24160000; in i740_calc_fifo()
283 wm = 0x18120000; in i740_calc_fifo()
285 wm = 0x16110000; in i740_calc_fifo()
287 wm = 0x13100000; in i740_calc_fifo()
290 wm = 0x311F0000; in i740_calc_fifo()
292 wm = 0x2C1D0000; in i740_calc_fifo()
294 wm = 0x25180000; in i740_calc_fifo()
296 wm = 0x24160000; in i740_calc_fifo()
298 wm = 0x18120000; in i740_calc_fifo()
300 wm = 0x16110000; in i740_calc_fifo()
302 wm = 0x13100000; in i740_calc_fifo()
308 wm = 0x2A200000; in i740_calc_fifo()
310 wm = 0x281A0000; in i740_calc_fifo()
312 wm = 0x25180000; in i740_calc_fifo()
314 wm = 0x18120000; in i740_calc_fifo()
316 wm = 0x16110000; in i740_calc_fifo()
319 wm = 0x29200000; in i740_calc_fifo()
321 wm = 0x281A0000; in i740_calc_fifo()
323 wm = 0x25180000; in i740_calc_fifo()
325 wm = 0x18120000; in i740_calc_fifo()
327 wm = 0x16110000; in i740_calc_fifo()
350 int m_best = 0, n_best = 0, p_best = 0; in i740_calc_vclk()
385 par->video_clk2_m = (m_best - 2) & 0xFF; in i740_calc_vclk()
386 par->video_clk2_n = (n_best - 2) & 0xFF; in i740_calc_vclk()
505 par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F) in i740fb_decode_var()
506 | ((((xres + right + hslen) >> 3) & 0x20) << 2); in i740fb_decode_var()
507 par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F) in i740fb_decode_var()
508 | 0x80; in i740fb_decode_var()
512 r7 = 0x10; /* disable linecompare */ in i740fb_decode_var()
513 if (ytotal & 0x100) in i740fb_decode_var()
514 r7 |= 0x01; in i740fb_decode_var()
515 if (ytotal & 0x200) in i740fb_decode_var()
516 r7 |= 0x20; in i740fb_decode_var()
518 par->crtc[VGA_CRTC_PRESET_ROW] = 0; in i740fb_decode_var()
519 par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */ in i740fb_decode_var()
521 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80; in i740fb_decode_var()
522 par->crtc[VGA_CRTC_CURSOR_START] = 0x00; in i740fb_decode_var()
523 par->crtc[VGA_CRTC_CURSOR_END] = 0x00; in i740fb_decode_var()
524 par->crtc[VGA_CRTC_CURSOR_HI] = 0x00; in i740fb_decode_var()
525 par->crtc[VGA_CRTC_CURSOR_LO] = 0x00; in i740fb_decode_var()
527 if ((yres-1) & 0x100) in i740fb_decode_var()
528 r7 |= 0x02; in i740fb_decode_var()
529 if ((yres-1) & 0x200) in i740fb_decode_var()
530 r7 |= 0x40; in i740fb_decode_var()
534 if ((yres + lower - 1) & 0x100) in i740fb_decode_var()
535 r7 |= 0x0C; in i740fb_decode_var()
536 if ((yres + lower - 1) & 0x200) { in i740fb_decode_var()
537 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20; in i740fb_decode_var()
538 r7 |= 0x80; in i740fb_decode_var()
543 ((yres + lower - 1 + vslen) & 0x0F) & ~0x10; in i740fb_decode_var()
544 /* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */ in i740fb_decode_var()
545 par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF; in i740fb_decode_var()
547 par->crtc[VGA_CRTC_UNDERLINE] = 0x00; in i740fb_decode_var()
548 par->crtc[VGA_CRTC_MODE] = 0xC3 ; in i740fb_decode_var()
549 par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF; in i740fb_decode_var()
552 par->vss = 0x00; /* 3DA */ in i740fb_decode_var()
554 for (i = 0x00; i < 0x10; i++) in i740fb_decode_var()
556 par->atc[VGA_ATC_MODE] = 0x81; in i740fb_decode_var()
557 par->atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */ in i740fb_decode_var()
558 par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F; in i740fb_decode_var()
559 par->atc[VGA_ATC_COLOR_PAGE] = 0x00; in i740fb_decode_var()
561 par->misc = 0xC3; in i740fb_decode_var()
563 par->misc &= ~0x40; in i740fb_decode_var()
565 par->misc &= ~0x80; in i740fb_decode_var()
567 par->seq[VGA_SEQ_CLOCK_MODE] = 0x01; in i740fb_decode_var()
568 par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F; in i740fb_decode_var()
569 par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00; in i740fb_decode_var()
570 par->seq[VGA_SEQ_MEMORY_MODE] = 0x06; in i740fb_decode_var()
572 par->gdc[VGA_GFX_SR_VALUE] = 0x00; in i740fb_decode_var()
573 par->gdc[VGA_GFX_SR_ENABLE] = 0x00; in i740fb_decode_var()
574 par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00; in i740fb_decode_var()
575 par->gdc[VGA_GFX_DATA_ROTATE] = 0x00; in i740fb_decode_var()
576 par->gdc[VGA_GFX_PLANE_READ] = 0; in i740fb_decode_var()
577 par->gdc[VGA_GFX_MODE] = 0x02; in i740fb_decode_var()
578 par->gdc[VGA_GFX_MISC] = 0x05; in i740fb_decode_var()
579 par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F; in i740fb_decode_var()
580 par->gdc[VGA_GFX_BIT_MASK] = 0xFF; in i740fb_decode_var()
590 case 15: /* 0rrrrrgg gggbbbbb */ in i740fb_decode_var()
604 base &= 0xFFFFFFFE; /* ...ignore the last bit. */ in i740fb_decode_var()
616 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF; in i740fb_decode_var()
617 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8; in i740fb_decode_var()
619 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE; in i740fb_decode_var()
620 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22; in i740fb_decode_var()
638 par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6; in i740fb_decode_var()
642 /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */ in i740fb_decode_var()
643 par->atc[VGA_ATC_OVERSCAN] = 0; in i740fb_decode_var()
654 par->misc |= 0x0C; in i740fb_decode_var()
660 return 0; in i740fb_decode_var()
670 var->red.offset = var->green.offset = var->blue.offset = 0; in i740fb_check_var()
679 var->blue.offset = 0; in i740fb_check_var()
687 var->blue.offset = 0; in i740fb_check_var()
695 var->blue.offset = 0; in i740fb_check_var()
702 var->blue.offset = 0; in i740fb_check_var()
717 info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) in i740fb_check_var()
720 return 0; in i740fb_check_var()
726 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20); in vga_protect()
728 i740inb(par, 0x3DA); in vga_protect()
729 i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */ in vga_protect()
735 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20); in vga_unprotect()
737 i740inb(par, 0x3DA); in vga_unprotect()
738 i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */ in vga_unprotect()
751 memset_io(info->screen_base, 0, info->screen_size); in i740fb_set_par()
765 par->pixelpipe_cfg0 & DAC_8_BIT, 0x80); in i740fb_set_par()
767 i740inb(par, 0x3DA); in i740fb_set_par()
768 i740outb(par, 0x3C0, 0x00); in i740fb_set_par()
771 i740outb(par, VGA_MIS_W, par->misc | 0x01); in i740fb_set_par()
774 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01); in i740fb_set_par()
777 par->seq[VGA_SEQ_CLOCK_MODE] | 0x20); in i740fb_set_par()
782 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03); in i740fb_set_par()
784 /* deprotect CRT registers 0-7 */ in i740fb_set_par()
789 for (i = 0; i < VGA_CRT_C; i++) in i740fb_set_par()
793 for (i = 0; i < VGA_GFX_C; i++) in i740fb_set_par()
797 for (i = 0; i < VGA_ATT_C; i++) { in i740fb_set_par()
804 i740outb(par, VGA_ATT_IW, 0x20); in i740fb_set_par()
820 i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F); in i740fb_set_par()
824 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B); in i740fb_set_par()
825 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C); in i740fb_set_par()
839 i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY); in i740fb_set_par()
844 i740outb(par, VGA_PEL_MSK, 0xFF); in i740fb_set_par()
845 i740outb(par, VGA_PEL_IW, 0x00); in i740fb_set_par()
846 for (i = 0; i < 256; i++) { in i740fb_set_par()
865 return 0; in i740fb_set_par()
901 return 0; in i740fb_setcolreg()
926 base &= 0xFFFFFFFE; /* ...ignore the last bit. */ in i740fb_pan_display()
934 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF; in i740fb_pan_display()
935 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8; in i740fb_pan_display()
936 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22; in i740fb_pan_display()
938 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE; in i740fb_pan_display()
940 i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO, base & 0x000000FF); in i740fb_pan_display()
942 (base & 0x0000FF00) >> 8); in i740fb_pan_display()
944 (base & 0x3FC00000) >> 22); in i740fb_pan_display()
946 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE); in i740fb_pan_display()
948 return 0; in i740fb_pan_display()
961 SEQ01 = 0x00; in i740fb_blank()
965 SEQ01 = 0x20; in i740fb_blank()
969 SEQ01 = 0x20; in i740fb_blank()
973 SEQ01 = 0x20; in i740fb_blank()
980 i740outb(par, SRX, 0x01); in i740fb_blank()
981 SEQ01 |= i740inb(par, SRX + 1) & ~0x20; in i740fb_blank()
982 i740outb(par, SRX, 0x01); in i740fb_blank()
989 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; in i740fb_blank()
1042 info->screen_base = pci_ioremap_wc_bar(dev, 0); in i740fb_probe()
1075 info->fix.smem_start = pci_resource_start(dev, 0); in i740fb_probe()
1079 if (i740fb_setup_ddc_bus(info) == 0) { in i740fb_probe()
1132 ret = fb_alloc_cmap(&info->cmap, 256, 0); in i740fb_probe()
1149 return 0; in i740fb_probe()
1197 if (par->ref_count == 0) { in i740fb_suspend()
1200 return 0; in i740fb_suspend()
1208 return 0; in i740fb_suspend()
1219 if (par->ref_count == 0) in i740fb_resume()
1223 fb_set_suspend(info, 0); in i740fb_resume()
1228 return 0; in i740fb_resume()
1242 #define I740_ID_PCI 0x00d1
1243 #define I740_ID_AGP 0x7800
1248 { 0 }
1266 return 0; in i740fb_setup()
1272 mtrr = simple_strtoul(opt + 5, NULL, 0); in i740fb_setup()
1277 return 0; in i740fb_setup()
1315 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");