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Searched +full:0 +full:x1a000000 (Results 1 – 6 of 6) sorted by relevance

/qemu/hw/mips/
H A Dloongson3_virt.c54 #define PM_CNTL_MODE 0x10
65 #define UART_IRQ 0
70 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
71 [VIRT_PM] = { 0x10080000, 0x100 },
72 [VIRT_FW_CFG] = { 0x10080100, 0x100 },
73 [VIRT_RTC] = { 0x10081000, 0x1000 },
74 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
75 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
76 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
77 [VIRT_UART] = { 0x1fe001e0, 0x8 },
[all …]
/qemu/hw/arm/
H A Dmusca.c110 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); in OBJECT_DECLARE_TYPE()
150 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); in make_unimp_dev()
170 .addr = 0x00200000,
171 .size = 0x00800000,
175 .addr = 0x00000000,
176 .size = 0x00200000,
183 .addr = 0x00000000,
184 .size = 0x02000000,
188 .addr = 0x0a400000,
189 .size = 0x00080000,
[all …]
H A Dintegratorcp.c58 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
59 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
86 if (offset >= 0x100 && offset < 0x200) { in integratorcm_read()
88 if (offset >= 0x180) in integratorcm_read()
89 return 0; in integratorcm_read()
93 case 0: /* CM_ID */ in integratorcm_read()
94 return 0x411a3001; in integratorcm_read()
96 return 0; in integratorcm_read()
102 return 0x00100000; in integratorcm_read()
104 if (s->cm_lock == 0xa05f) { in integratorcm_read()
[all …]
H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
56 /* Number of virtio transports to create (0..8; limited by
100 [VE_NORFLASHALIAS] = 0,
101 /* CS7: 0x10000000 .. 0x10020000 */
102 [VE_SYSREGS] = 0x10000000,
103 [VE_SP810] = 0x10001000,
104 [VE_SERIALPCI] = 0x10002000,
105 [VE_PL041] = 0x10004000,
106 [VE_MMCI] = 0x10005000,
107 [VE_KMI0] = 0x10006000,
[all …]
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc18 #define TCG_TARGET_CALL_STACK_OFFSET 0
31 QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
82 tcg_debug_assert(slot >= 0 && slot <= 1);
98 if (offset == sextract64(offset, 0, 26)) {
101 *src_rw = deposit32(*src_rw, 0, 26, offset);
112 if (offset == sextract64(offset, 0, 19)) {
124 if (offset == sextract64(offset, 0, 14)) {
134 tcg_debug_assert(addend == 0);
148 #define TCG_CT_CONST_AIMM 0x100
149 #define TCG_CT_CONST_LIMM 0x200
[all …]
/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
[all …]