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/linux-6.15/drivers/regulator/
Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/linux-6.15/arch/arm/mach-omap2/
Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/linux-6.15/drivers/net/ethernet/qualcomm/
Dqca_7k.h21 #define QCA7K_SPI_WRITE (0 << 15)
23 #define QCA7K_SPI_EXTERNAL (0 << 14)
27 #define QCASPI_HW_BUF_LEN 0xC5B
30 #define SPI_REG_BFR_SIZE 0x0100
31 #define SPI_REG_WRBUF_SPC_AVA 0x0200
32 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
33 #define SPI_REG_SPI_CONFIG 0x0400
34 #define SPI_REG_SPI_STATUS 0x0500
35 #define SPI_REG_INTR_CAUSE 0x0C00
36 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/linux-6.15/sound/soc/amd/acp/
Dacp-legacy-common.c22 #define ACP_RENOIR_PDM_ADDR 0x02
23 #define ACP_REMBRANDT_PDM_ADDR 0x03
24 #define ACP63_PDM_ADDR 0x02
25 #define ACP70_PDM_ADDR 0x02
30 .irqp_used = 0,
31 .irq_reg_offset = 0x1800,
32 .scratch_reg_offset = 0x12800,
33 .sram_pte_offset = 0x02052800,
38 .offset = 0,
42 .irq_reg_offset = 0x1a00,
[all …]
/linux-6.15/sound/soc/sof/amd/
Dacp-dsp-offset.h15 #define ACP_DMA_CNTL_0 0x00
16 #define ACP_DMA_DSCR_STRT_IDX_0 0x20
17 #define ACP_DMA_DSCR_CNT_0 0x40
18 #define ACP_DMA_PRIO_0 0x60
19 #define ACP_DMA_CUR_DSCR_0 0x80
20 #define ACP_DMA_ERR_STS_0 0xC0
21 #define ACP_DMA_DESC_BASE_ADDR 0xE0
22 #define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4
23 #define ACP_DMA_CH_STS 0xE8
24 #define ACP_DMA_CH_GROUP 0xEC
[all …]
/linux-6.15/drivers/net/wireless/broadcom/b43/
Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
/linux-6.15/arch/arm/boot/dts/ti/omap/
Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
/linux-6.15/drivers/block/
Dswim_asm.S17 .equ write_data, 0x0000
18 .equ write_mark, 0x0200
19 .equ write_CRC, 0x0400
20 .equ write_parameter,0x0600
21 .equ write_phase, 0x0800
22 .equ write_setup, 0x0a00
23 .equ write_mode0, 0x0c00
24 .equ write_mode1, 0x0e00
25 .equ read_data, 0x1000
26 .equ read_mark, 0x1200
[all …]
/linux-6.15/drivers/net/ethernet/tehuti/
Dtn40_regs.h8 #define TN40_REGS_SIZE 0x10000
10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
11 #define TN40_REG_TXD_CFG1_0 0x4000
12 #define TN40_REG_TXD_CFG1_1 0x4004
13 #define TN40_REG_TXD_CFG1_2 0x4008
14 #define TN40_REG_TXD_CFG1_3 0x400C
16 #define TN40_REG_RXF_CFG1_0 0x4010
17 #define TN40_REG_RXF_CFG1_1 0x4014
18 #define TN40_REG_RXF_CFG1_2 0x4018
19 #define TN40_REG_RXF_CFG1_3 0x401C
[all …]
/linux-6.15/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_5_4_sm6125.h13 .max_mixer_blendstages = 0x6,
24 .base = 0x0, .len = 0x45c,
25 .features = 0,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
37 .base = 0x1000, .len = 0x1e0,
42 .base = 0x1200, .len = 0x1e0,
47 .base = 0x1400, .len = 0x1e0,
[all …]
Ddpu_5_3_sm6150.h11 .max_mixer_blendstages = 0x9,
22 .base = 0x0, .len = 0x45c,
23 .features = 0,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
30 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
37 .base = 0x1000, .len = 0x1e0,
[all …]
Ddpu_5_2_sm7150.h12 .max_mixer_blendstages = 0xb,
25 .base = 0x0, .len = 0x45c,
28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
40 .base = 0x1000, .len = 0x1e0,
45 .base = 0x1200, .len = 0x1e0,
[all …]
/linux-6.15/drivers/net/wireless/broadcom/b43legacy/
Dradio.c30 0x0002, 0x0003, 0x0001, 0x000F,
31 0x0006, 0x0007, 0x0005, 0x000F,
32 0x000A, 0x000B, 0x0009, 0x000F,
33 0x000E, 0x000F, 0x000D, 0x000F,
41 u16 flipped = 0x0000; in flip_4bit()
43 B43legacy_BUG_ON(!((value & ~0x000F) == 0x0000)); in flip_4bit()
45 flipped |= (value & 0x0001) << 3; in flip_4bit()
46 flipped |= (value & 0x0002) << 1; in flip_4bit()
47 flipped |= (value & 0x0004) >> 1; in flip_4bit()
48 flipped |= (value & 0x0008) >> 3; in flip_4bit()
[all …]
/linux-6.15/arch/x86/boot/
Dvideo-vga.c18 { VIDEO_80x25, 80, 25, 0 },
19 { VIDEO_8POINT, 80, 50, 0 },
20 { VIDEO_80x43, 80, 43, 0 },
21 { VIDEO_80x28, 80, 28, 0 },
22 { VIDEO_80x30, 80, 30, 0 },
23 { VIDEO_80x34, 80, 34, 0 },
24 { VIDEO_80x60, 80, 60, 0 },
28 { VIDEO_80x25, 80, 25, 0 },
29 { VIDEO_8POINT, 80, 43, 0 },
33 { VIDEO_80x25, 80, 25, 0 },
[all …]
/linux-6.15/arch/arm/plat-orion/
Dpcie.c22 #define PCIE_DEV_ID_OFF 0x0000
23 #define PCIE_CMD_OFF 0x0004
24 #define PCIE_DEV_REV_OFF 0x0008
25 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
26 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
27 #define PCIE_HEADER_LOG_4_OFF 0x0128
28 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
29 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
30 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
31 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
[all …]
/linux-6.15/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/linux-6.15/include/video/
Daty128.h13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
/linux-6.15/drivers/net/ethernet/microchip/
Denc28j60_hw.h15 * - Register address (bits 0-4)
19 #define ADDR_MASK 0x1F
20 #define BANK_MASK 0x60
21 #define SPRD_MASK 0x80
23 #define EIE 0x1B
24 #define EIR 0x1C
25 #define ESTAT 0x1D
26 #define ECON2 0x1E
27 #define ECON1 0x1F
28 /* Bank 0 registers */
[all …]
/linux-6.15/drivers/media/platform/qcom/camss/
Dcamss-vfe-480.c18 #define VFE_GLOBAL_RESET_CMD (vfe_is_lite(vfe) ? 0x0c : 0x1c)
19 #define GLOBAL_RESET_HW_AND_REG (vfe_is_lite(vfe) ? BIT(1) : BIT(0))
21 #define VFE_REG_UPDATE_CMD (vfe_is_lite(vfe) ? 0x20 : 0x34)
28 #define VFE_IRQ_CMD (vfe_is_lite(vfe) ? 0x24 : 0x38)
29 #define IRQ_CMD_GLOBAL_CLEAR BIT(0)
31 #define VFE_IRQ_MASK(n) ((vfe_is_lite(vfe) ? 0x28 : 0x3c) + (n) * 4)
32 #define IRQ_MASK_0_RESET_ACK (vfe_is_lite(vfe) ? BIT(17) : BIT(0))
34 #define VFE_IRQ_CLEAR(n) ((vfe_is_lite(vfe) ? 0x34 : 0x48) + (n) * 4)
35 #define VFE_IRQ_STATUS(n) ((vfe_is_lite(vfe) ? 0x40 : 0x54) + (n) * 4)
37 #define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x1a00 : 0xaa00)
[all …]
/linux-6.15/drivers/scsi/fnic/
Dfnic_fdls.h65 * bits 0-8: oxid idx - allocated from poool
71 #define FNIC_FRAME_MASK 0xFE00
77 #define FNIC_FDLS_FABRIC_ABORT_ISSUED 0x1
78 #define FNIC_FDLS_FPMA_LEARNT 0x2
81 #define FNIC_FDLS_TPORT_IN_GPN_FT_LIST 0x1
82 #define FNIC_FDLS_TGT_ABORT_ISSUED 0x2
83 #define FNIC_FDLS_TPORT_SEND_ADISC 0x4
84 #define FNIC_FDLS_RETRY_FRAME 0x8
85 #define FNIC_FDLS_TPORT_BUSY 0x10
86 #define FNIC_FDLS_TPORT_TERMINATING 0x20
[all …]
/linux-6.15/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.c278 .base = 0xa00, .len = 0xa0,}, \
280 .base = 0x1a00, .len = 0x100,}, \
290 .base = 0xa00, .len = 0xa0,}, \
292 .base = 0x1a00, .len = 0x100,}, \
309 .base = 0x200, .len = 0xa0,}, \
311 .base = 0x320, .len = 0x100,}, \
320 .base = 0x200, .len = 0x28,}, \
356 _VIG_SBLK(SSPP_SCALER_VER(3, 0));
359 _VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0),
385 0x20, 0x50, 0x80, 0xb0, 0x230,
[all …]
/linux-6.15/drivers/net/ethernet/sis/
Dsis190.c40 #define PHY_ID_ANY 0x1f
41 #define MII_REG_ANY 0x1f
55 #define RX_BUF_MASK 0xfff8
57 #define SIS190_REGS_SIZE 0x80
65 #define EhnMIIread 0x0000
66 #define EhnMIIwrite 0x0020
70 #define EhnMIIreq 0x0010
71 #define EhnMIInotDone 0x0010
84 TxControl = 0x00,
85 TxDescStartAddr = 0x04,
[all …]
/linux-6.15/drivers/media/i2c/
Dhi847.c25 #define HI847_REG_CHIP_ID 0x0716
26 #define HI847_CHIP_ID 0x0847
28 #define HI847_REG_MODE_SELECT 0x0B00
29 #define HI847_MODE_STANDBY 0x0000
30 #define HI847_MODE_STREAMING 0x0100
32 #define HI847_REG_MODE_TG 0x027E
33 #define HI847_REG_MODE_TG_ENABLE 0x0100
34 #define HI847_REG_MODE_TG_DISABLE 0x0000
37 #define HI847_REG_FLL 0x020E
38 #define HI847_FLL_30FPS 0x0B51
[all …]

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