18 #define VFE_GLOBAL_RESET_CMD		(vfe_is_lite(vfe) ? 0x0c : 0x1c)
19 #define	    GLOBAL_RESET_HW_AND_REG	(vfe_is_lite(vfe) ? BIT(1) : BIT(0))
21 #define VFE_REG_UPDATE_CMD		(vfe_is_lite(vfe) ? 0x20 : 0x34)
28 #define VFE_IRQ_CMD			(vfe_is_lite(vfe) ? 0x24 : 0x38)
29 #define     IRQ_CMD_GLOBAL_CLEAR	BIT(0)
31 #define VFE_IRQ_MASK(n)			((vfe_is_lite(vfe) ? 0x28 : 0x3c) + (n) * 4)
32 #define	    IRQ_MASK_0_RESET_ACK	(vfe_is_lite(vfe) ? BIT(17) : BIT(0))
34 #define VFE_IRQ_CLEAR(n)		((vfe_is_lite(vfe) ? 0x34 : 0x48) + (n) * 4)
35 #define VFE_IRQ_STATUS(n)		((vfe_is_lite(vfe) ? 0x40 : 0x54) + (n) * 4)
37 #define BUS_REG_BASE			(vfe_is_lite(vfe) ? 0x1a00 : 0xaa00)
39 #define VFE_BUS_WM_CGC_OVERRIDE		(BUS_REG_BASE + 0x08)
40 #define		WM_CGC_OVERRIDE_ALL	(0x3FFFFFF)
42 #define VFE_BUS_WM_TEST_BUS_CTRL	(BUS_REG_BASE + 0xdc)
44 #define VFE_BUS_IRQ_MASK(n)		(BUS_REG_BASE + 0x18 + (n) * 4)
57 #define VFE_BUS_IRQ_CLEAR(n)		(BUS_REG_BASE + 0x20 + (n) * 4)
58 #define VFE_BUS_IRQ_STATUS(n)		(BUS_REG_BASE + 0x28 + (n) * 4)
59 #define VFE_BUS_IRQ_CLEAR_GLOBAL	(BUS_REG_BASE + 0x30)
61 #define VFE_BUS_WM_CFG(n)		(BUS_REG_BASE + 0x200 + (n) * 0x100)
62 #define		WM_CFG_EN			(0)
64 #define			MODE_QCOM_PLAIN	(0)
66 #define VFE_BUS_WM_IMAGE_ADDR(n)	(BUS_REG_BASE + 0x204 + (n) * 0x100)
67 #define VFE_BUS_WM_FRAME_INCR(n)	(BUS_REG_BASE + 0x208 + (n) * 0x100)
68 #define VFE_BUS_WM_IMAGE_CFG_0(n)	(BUS_REG_BASE + 0x20c + (n) * 0x100)
69 #define		WM_IMAGE_CFG_0_DEFAULT_WIDTH	(0xFFFF)
70 #define VFE_BUS_WM_IMAGE_CFG_1(n)	(BUS_REG_BASE + 0x210 + (n) * 0x100)
71 #define VFE_BUS_WM_IMAGE_CFG_2(n)	(BUS_REG_BASE + 0x214 + (n) * 0x100)
72 #define VFE_BUS_WM_PACKER_CFG(n)	(BUS_REG_BASE + 0x218 + (n) * 0x100)
73 #define VFE_BUS_WM_HEADER_ADDR(n)	(BUS_REG_BASE + 0x220 + (n) * 0x100)
74 #define VFE_BUS_WM_HEADER_INCR(n)	(BUS_REG_BASE + 0x224 + (n) * 0x100)
75 #define VFE_BUS_WM_HEADER_CFG(n)	(BUS_REG_BASE + 0x228 + (n) * 0x100)
77 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n)	(BUS_REG_BASE + 0x230 + (n) * 0x100)
78 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n)	(BUS_REG_BASE + 0x234 + (n) * 0x100)
79 #define VFE_BUS_WM_FRAMEDROP_PERIOD(n)		(BUS_REG_BASE + 0x238 + (n) * 0x100)
80 #define VFE_BUS_WM_FRAMEDROP_PATTERN(n)		(BUS_REG_BASE + 0x23c + (n) * 0x100)
82 #define VFE_BUS_WM_SYSTEM_CACHE_CFG(n)	(BUS_REG_BASE + 0x260 + (n) * 0x100)
83 #define VFE_BUS_WM_BURST_LIMIT(n)	(BUS_REG_BASE + 0x264 + (n) * 0x100)
88 #define RDI_WM(n)			((vfe_is_lite(vfe) ? 0 : 23) + (n))
89 #define RDI_COMP_GROUP(n)		((vfe_is_lite(vfe) ? 0 : 11) + (n))
95 	writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0));  in vfe_global_reset()
109 	writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);  in vfe_wm_start()
111 	writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height,  in vfe_wm_start()
113 	writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));  in vfe_wm_start()
116 	writel_relaxed(pix->plane_fmt[0].bytesperline,  in vfe_wm_start()
118 	writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));  in vfe_wm_start()
121 	writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));  in vfe_wm_start()
123 	writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));  in vfe_wm_start()
133 	writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));  in vfe_wm_stop()
158 	u32 bus_irq_mask = 0;  in vfe_enable_irq()
163 		       vfe->base + VFE_IRQ_MASK(0));  in vfe_enable_irq()
165 	for (i = 0; i < MAX_VFE_OUTPUT_LINES; i++) {  in vfe_enable_irq()
174 	writel(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0));  in vfe_enable_irq()
192 	status = readl_relaxed(vfe->base + VFE_IRQ_STATUS(0));  in vfe_isr()
193 	writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0));  in vfe_isr()
200 		u32 status = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(0));  in vfe_isr()
202 		writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0));  in vfe_isr()
206 		for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) {  in vfe_isr()
222  * Return 0 on success or a negative error code otherwise
227 	return 0;  in vfe_halt()
246 		output->wait_reg_update = 0;  in vfe_isr_reg_update()