1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_BASE_MASK \ 16 (BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MASK \ 21 (VIG_BASE_MASK | \ 22 BIT(DPU_SSPP_CSC_10BIT)) 23 24 #define VIG_MSM8953_MASK \ 25 (BIT(DPU_SSPP_QOS) |\ 26 BIT(DPU_SSPP_SCALER_QSEED2) |\ 27 BIT(DPU_SSPP_CSC)) 28 29 #define VIG_MSM8996_MASK \ 30 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ 31 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_QSEED2) |\ 32 BIT(DPU_SSPP_CSC)) 33 34 #define VIG_MSM8998_MASK \ 35 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 36 37 #define VIG_SDM845_MASK \ 38 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 39 40 #define VIG_SDM845_MASK_SDMA \ 41 (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 42 43 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) 44 45 #define DMA_MSM8953_MASK \ 46 (BIT(DPU_SSPP_QOS)) 47 48 #define DMA_MSM8996_MASK \ 49 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_CDP)) 50 51 #define DMA_MSM8998_MASK \ 52 (BIT(DPU_SSPP_QOS) |\ 53 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 54 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 55 56 #define VIG_SC7280_MASK \ 57 (VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 58 59 #define VIG_SC7280_MASK_SDMA \ 60 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 61 62 #define DMA_SDM845_MASK \ 63 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 64 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 65 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 66 67 #define DMA_CURSOR_SDM845_MASK \ 68 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 69 70 #define DMA_SDM845_MASK_SDMA \ 71 (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 72 73 #define DMA_CURSOR_SDM845_MASK_SDMA \ 74 (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 75 76 #define DMA_CURSOR_MSM8996_MASK \ 77 (DMA_MSM8996_MASK | BIT(DPU_SSPP_CURSOR)) 78 79 #define DMA_CURSOR_MSM8998_MASK \ 80 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 81 82 #define RGB_MSM8953_MASK \ 83 (BIT(DPU_SSPP_QOS)) 84 85 #define RGB_MSM8996_MASK \ 86 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ 87 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_RGB)) 88 89 #define MIXER_MSM8998_MASK \ 90 (BIT(DPU_MIXER_SOURCESPLIT)) 91 92 #define MIXER_SDM845_MASK \ 93 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 94 95 #define MIXER_QCM2290_MASK \ 96 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 97 98 #define PINGPONG_MSM8996_MASK \ 99 (BIT(DPU_PINGPONG_DSC)) 100 101 #define PINGPONG_MSM8996_TE2_MASK \ 102 (PINGPONG_MSM8996_MASK | BIT(DPU_PINGPONG_TE2)) 103 104 #define PINGPONG_SDM845_MASK \ 105 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 106 107 #define PINGPONG_SDM845_TE2_MASK \ 108 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 109 110 #define PINGPONG_SM8150_MASK \ 111 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 112 113 #define CTL_SC7280_MASK \ 114 (BIT(DPU_CTL_ACTIVE_CFG) | \ 115 BIT(DPU_CTL_FETCH_ACTIVE) | \ 116 BIT(DPU_CTL_VM_CFG) | \ 117 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 118 119 #define CTL_SM8550_MASK \ 120 (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) 121 122 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 123 124 #define INTF_SC7180_MASK \ 125 (BIT(DPU_INTF_INPUT_CTRL) | \ 126 BIT(DPU_INTF_STATUS_SUPPORTED) | \ 127 BIT(DPU_DATA_HCTL_EN)) 128 129 #define INTF_SC7280_MASK (INTF_SC7180_MASK) 130 131 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ 132 BIT(DPU_WB_UBWC) | \ 133 BIT(DPU_WB_YUV_CONFIG) | \ 134 BIT(DPU_WB_PIPE_ALPHA) | \ 135 BIT(DPU_WB_XY_ROI_OFFSET) | \ 136 BIT(DPU_WB_QOS) | \ 137 BIT(DPU_WB_QOS_8LVL) | \ 138 BIT(DPU_WB_CDP)) 139 140 #define WB_SM8250_MASK (WB_SDM845_MASK | \ 141 BIT(DPU_WB_INPUT_CTRL)) 142 143 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 144 #define DEFAULT_DPU_LINE_WIDTH 2048 145 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 146 147 #define MAX_HORZ_DECIMATION 4 148 #define MAX_VERT_DECIMATION 4 149 150 #define STRCAT(X, Y) (X Y) 151 152 static const uint32_t plane_formats[] = { 153 DRM_FORMAT_ARGB8888, 154 DRM_FORMAT_ABGR8888, 155 DRM_FORMAT_RGBA8888, 156 DRM_FORMAT_BGRA8888, 157 DRM_FORMAT_XRGB8888, 158 DRM_FORMAT_RGBX8888, 159 DRM_FORMAT_BGRX8888, 160 DRM_FORMAT_XBGR8888, 161 DRM_FORMAT_ARGB2101010, 162 DRM_FORMAT_XRGB2101010, 163 DRM_FORMAT_RGB888, 164 DRM_FORMAT_BGR888, 165 DRM_FORMAT_RGB565, 166 DRM_FORMAT_BGR565, 167 DRM_FORMAT_ARGB1555, 168 DRM_FORMAT_ABGR1555, 169 DRM_FORMAT_RGBA5551, 170 DRM_FORMAT_BGRA5551, 171 DRM_FORMAT_XRGB1555, 172 DRM_FORMAT_XBGR1555, 173 DRM_FORMAT_RGBX5551, 174 DRM_FORMAT_BGRX5551, 175 DRM_FORMAT_ARGB4444, 176 DRM_FORMAT_ABGR4444, 177 DRM_FORMAT_RGBA4444, 178 DRM_FORMAT_BGRA4444, 179 DRM_FORMAT_XRGB4444, 180 DRM_FORMAT_XBGR4444, 181 DRM_FORMAT_RGBX4444, 182 DRM_FORMAT_BGRX4444, 183 }; 184 185 static const uint32_t plane_formats_yuv[] = { 186 DRM_FORMAT_ARGB8888, 187 DRM_FORMAT_ABGR8888, 188 DRM_FORMAT_RGBA8888, 189 DRM_FORMAT_BGRX8888, 190 DRM_FORMAT_BGRA8888, 191 DRM_FORMAT_ARGB2101010, 192 DRM_FORMAT_XRGB2101010, 193 DRM_FORMAT_XRGB8888, 194 DRM_FORMAT_XBGR8888, 195 DRM_FORMAT_RGBX8888, 196 DRM_FORMAT_RGB888, 197 DRM_FORMAT_BGR888, 198 DRM_FORMAT_RGB565, 199 DRM_FORMAT_BGR565, 200 DRM_FORMAT_ARGB1555, 201 DRM_FORMAT_ABGR1555, 202 DRM_FORMAT_RGBA5551, 203 DRM_FORMAT_BGRA5551, 204 DRM_FORMAT_XRGB1555, 205 DRM_FORMAT_XBGR1555, 206 DRM_FORMAT_RGBX5551, 207 DRM_FORMAT_BGRX5551, 208 DRM_FORMAT_ARGB4444, 209 DRM_FORMAT_ABGR4444, 210 DRM_FORMAT_RGBA4444, 211 DRM_FORMAT_BGRA4444, 212 DRM_FORMAT_XRGB4444, 213 DRM_FORMAT_XBGR4444, 214 DRM_FORMAT_RGBX4444, 215 DRM_FORMAT_BGRX4444, 216 217 DRM_FORMAT_P010, 218 DRM_FORMAT_NV12, 219 DRM_FORMAT_NV21, 220 DRM_FORMAT_NV16, 221 DRM_FORMAT_NV61, 222 DRM_FORMAT_VYUY, 223 DRM_FORMAT_UYVY, 224 DRM_FORMAT_YUYV, 225 DRM_FORMAT_YVYU, 226 DRM_FORMAT_YUV420, 227 DRM_FORMAT_YVU420, 228 }; 229 230 static const u32 rotation_v2_formats[] = { 231 DRM_FORMAT_NV12, 232 /* TODO add formats after validation */ 233 }; 234 235 static const u32 wb2_formats_rgb_yuv[] = { 236 DRM_FORMAT_RGB565, 237 DRM_FORMAT_BGR565, 238 DRM_FORMAT_RGB888, 239 DRM_FORMAT_ARGB8888, 240 DRM_FORMAT_RGBA8888, 241 DRM_FORMAT_ABGR8888, 242 DRM_FORMAT_XRGB8888, 243 DRM_FORMAT_RGBX8888, 244 DRM_FORMAT_XBGR8888, 245 DRM_FORMAT_ARGB1555, 246 DRM_FORMAT_RGBA5551, 247 DRM_FORMAT_XRGB1555, 248 DRM_FORMAT_RGBX5551, 249 DRM_FORMAT_ARGB4444, 250 DRM_FORMAT_RGBA4444, 251 DRM_FORMAT_RGBX4444, 252 DRM_FORMAT_XRGB4444, 253 DRM_FORMAT_BGR888, 254 DRM_FORMAT_BGRA8888, 255 DRM_FORMAT_BGRX8888, 256 DRM_FORMAT_ABGR1555, 257 DRM_FORMAT_BGRA5551, 258 DRM_FORMAT_XBGR1555, 259 DRM_FORMAT_BGRX5551, 260 DRM_FORMAT_ABGR4444, 261 DRM_FORMAT_BGRA4444, 262 DRM_FORMAT_BGRX4444, 263 DRM_FORMAT_XBGR4444, 264 DRM_FORMAT_NV12, 265 }; 266 267 /************************************************************* 268 * SSPP sub blocks config 269 *************************************************************/ 270 271 #define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min)) 272 273 /* SSPP common configuration */ 274 #define _VIG_SBLK(scaler_ver) \ 275 { \ 276 .scaler_blk = {.name = "scaler", \ 277 .version = scaler_ver, \ 278 .base = 0xa00, .len = 0xa0,}, \ 279 .csc_blk = {.name = "csc", \ 280 .base = 0x1a00, .len = 0x100,}, \ 281 .format_list = plane_formats_yuv, \ 282 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 283 .rotation_cfg = NULL, \ 284 } 285 286 #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ 287 { \ 288 .scaler_blk = {.name = "scaler", \ 289 .version = scaler_ver, \ 290 .base = 0xa00, .len = 0xa0,}, \ 291 .csc_blk = {.name = "csc", \ 292 .base = 0x1a00, .len = 0x100,}, \ 293 .format_list = plane_formats_yuv, \ 294 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 295 .rotation_cfg = rot_cfg, \ 296 } 297 298 #define _VIG_SBLK_NOSCALE() \ 299 { \ 300 .format_list = plane_formats, \ 301 .num_formats = ARRAY_SIZE(plane_formats), \ 302 } 303 304 /* qseed2 is not supported, so disabled scaling */ 305 #define _VIG_SBLK_QSEED2() \ 306 { \ 307 .scaler_blk = {.name = "scaler", \ 308 /* no version for qseed2 */ \ 309 .base = 0x200, .len = 0xa0,}, \ 310 .csc_blk = {.name = "csc", \ 311 .base = 0x320, .len = 0x100,}, \ 312 .format_list = plane_formats_yuv, \ 313 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 314 .rotation_cfg = NULL, \ 315 } 316 317 #define _RGB_SBLK() \ 318 { \ 319 .scaler_blk = {.name = "scaler", \ 320 .base = 0x200, .len = 0x28,}, \ 321 .format_list = plane_formats, \ 322 .num_formats = ARRAY_SIZE(plane_formats), \ 323 } 324 325 #define _DMA_SBLK() \ 326 { \ 327 .format_list = plane_formats, \ 328 .num_formats = ARRAY_SIZE(plane_formats), \ 329 } 330 331 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 332 .rot_maxheight = 1088, 333 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 334 .rot_format_list = rotation_v2_formats, 335 }; 336 337 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed2 = 338 _VIG_SBLK_QSEED2(); 339 340 static const struct dpu_sspp_sub_blks dpu_vig_sblk_noscale = 341 _VIG_SBLK_NOSCALE(); 342 343 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_2 = 344 _VIG_SBLK(SSPP_SCALER_VER(1, 2)); 345 346 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_3 = 347 _VIG_SBLK(SSPP_SCALER_VER(1, 3)); 348 349 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_4 = 350 _VIG_SBLK(SSPP_SCALER_VER(1, 4)); 351 352 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_2_4 = 353 _VIG_SBLK(SSPP_SCALER_VER(2, 4)); 354 355 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0 = 356 _VIG_SBLK(SSPP_SCALER_VER(3, 0)); 357 358 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0_rot_v2 = 359 _VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0), 360 &dpu_rot_sc7280_cfg_v2); 361 362 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_1 = 363 _VIG_SBLK(SSPP_SCALER_VER(3, 1)); 364 365 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 = 366 _VIG_SBLK(SSPP_SCALER_VER(3, 2)); 367 368 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 = 369 _VIG_SBLK(SSPP_SCALER_VER(3, 3)); 370 371 static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK(); 372 373 static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK(); 374 375 /************************************************************* 376 * MIXER sub blocks config 377 *************************************************************/ 378 379 /* MSM8998 */ 380 381 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 382 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 383 .maxblendstages = 7, /* excluding base layer */ 384 .blendstage_base = { /* offsets relative to mixer base */ 385 0x20, 0x50, 0x80, 0xb0, 0x230, 386 0x260, 0x290 387 }, 388 }; 389 390 /* SDM845 */ 391 392 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 393 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 394 .maxblendstages = 11, /* excluding base layer */ 395 .blendstage_base = { /* offsets relative to mixer base */ 396 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 397 0xb0, 0xc8, 0xe0, 0xf8, 0x110 398 }, 399 }; 400 401 /* SC7180 */ 402 403 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 404 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 405 .maxblendstages = 7, /* excluding base layer */ 406 .blendstage_base = { /* offsets relative to mixer base */ 407 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 408 }, 409 }; 410 411 /* QCM2290 */ 412 413 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 414 .maxwidth = DEFAULT_DPU_LINE_WIDTH, 415 .maxblendstages = 4, /* excluding base layer */ 416 .blendstage_base = { /* offsets relative to mixer base */ 417 0x20, 0x38, 0x50, 0x68 418 }, 419 }; 420 421 /************************************************************* 422 * DSPP sub blocks config 423 *************************************************************/ 424 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 425 .pcc = {.name = "pcc", .base = 0x1700, 426 .len = 0x90, .version = 0x10007}, 427 }; 428 429 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { 430 .pcc = {.name = "pcc", .base = 0x1700, 431 .len = 0x90, .version = 0x40000}, 432 }; 433 434 /************************************************************* 435 * PINGPONG sub blocks config 436 *************************************************************/ 437 static const struct dpu_pingpong_sub_blks msm8996_pp_sblk_te = { 438 .te2 = {.name = "te2", .base = 0x2000, .len = 0x0, 439 .version = 0x1}, 440 }; 441 442 static const struct dpu_pingpong_sub_blks msm8996_pp_sblk = { 443 /* No dither block */ 444 }; 445 446 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 447 .te2 = {.name = "te2", .base = 0x2000, .len = 0x0, 448 .version = 0x1}, 449 .dither = {.name = "dither", .base = 0x30e0, 450 .len = 0x20, .version = 0x10000}, 451 }; 452 453 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 454 .dither = {.name = "dither", .base = 0x30e0, 455 .len = 0x20, .version = 0x10000}, 456 }; 457 458 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 459 .dither = {.name = "dither", .base = 0xe0, 460 .len = 0x20, .version = 0x20000}, 461 }; 462 463 /************************************************************* 464 * DSC sub blocks config 465 *************************************************************/ 466 static const struct dpu_dsc_sub_blks dsc_sblk_0 = { 467 .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, 468 .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, 469 }; 470 471 static const struct dpu_dsc_sub_blks dsc_sblk_1 = { 472 .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, 473 .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, 474 }; 475 476 /************************************************************* 477 * CDM block config 478 *************************************************************/ 479 static const struct dpu_cdm_cfg dpu_cdm_1_x_4_x = { 480 .name = "cdm_0", 481 .id = CDM_0, 482 .len = 0x224, 483 .base = 0x79200, 484 }; 485 486 static const struct dpu_cdm_cfg dpu_cdm_5_x = { 487 .name = "cdm_0", 488 .id = CDM_0, 489 .len = 0x228, 490 .base = 0x79200, 491 }; 492 493 /************************************************************* 494 * VBIF sub blocks config 495 *************************************************************/ 496 /* VBIF QOS remap */ 497 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 498 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 499 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 500 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 501 static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 5, 6}; 502 503 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 504 { 505 .pps = 1920 * 1080 * 30, 506 .ot_limit = 2, 507 }, 508 { 509 .pps = 1920 * 1080 * 60, 510 .ot_limit = 4, 511 }, 512 { 513 .pps = 3840 * 2160 * 30, 514 .ot_limit = 16, 515 }, 516 }; 517 518 static const struct dpu_vbif_cfg msm8996_vbif[] = { 519 { 520 .name = "vbif_rt", .id = VBIF_RT, 521 .base = 0, .len = 0x1040, 522 .default_ot_rd_limit = 32, 523 .default_ot_wr_limit = 16, 524 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 525 .xin_halt_timeout = 0x4000, 526 .qos_rp_remap_size = 0x20, 527 .dynamic_ot_rd_tbl = { 528 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 529 .cfg = msm8998_ot_rdwr_cfg, 530 }, 531 .dynamic_ot_wr_tbl = { 532 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 533 .cfg = msm8998_ot_rdwr_cfg, 534 }, 535 .qos_rt_tbl = { 536 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 537 .priority_lvl = msm8998_rt_pri_lvl, 538 }, 539 .qos_nrt_tbl = { 540 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 541 .priority_lvl = msm8998_nrt_pri_lvl, 542 }, 543 }, 544 }; 545 546 static const struct dpu_vbif_cfg msm8998_vbif[] = { 547 { 548 .name = "vbif_rt", .id = VBIF_RT, 549 .base = 0, .len = 0x1040, 550 .default_ot_rd_limit = 32, 551 .default_ot_wr_limit = 32, 552 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 553 .xin_halt_timeout = 0x4000, 554 .qos_rp_remap_size = 0x20, 555 .dynamic_ot_rd_tbl = { 556 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 557 .cfg = msm8998_ot_rdwr_cfg, 558 }, 559 .dynamic_ot_wr_tbl = { 560 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 561 .cfg = msm8998_ot_rdwr_cfg, 562 }, 563 .qos_rt_tbl = { 564 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 565 .priority_lvl = msm8998_rt_pri_lvl, 566 }, 567 .qos_nrt_tbl = { 568 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 569 .priority_lvl = msm8998_nrt_pri_lvl, 570 }, 571 .memtype_count = 14, 572 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 573 }, 574 }; 575 576 static const struct dpu_vbif_cfg sdm845_vbif[] = { 577 { 578 .name = "vbif_rt", .id = VBIF_RT, 579 .base = 0, .len = 0x1040, 580 .features = BIT(DPU_VBIF_QOS_REMAP), 581 .xin_halt_timeout = 0x4000, 582 .qos_rp_remap_size = 0x40, 583 .qos_rt_tbl = { 584 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 585 .priority_lvl = sdm845_rt_pri_lvl, 586 }, 587 .qos_nrt_tbl = { 588 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 589 .priority_lvl = sdm845_nrt_pri_lvl, 590 }, 591 .memtype_count = 14, 592 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 593 }, 594 }; 595 596 static const struct dpu_vbif_cfg sm8550_vbif[] = { 597 { 598 .name = "vbif_rt", .id = VBIF_RT, 599 .base = 0, .len = 0x1040, 600 .features = BIT(DPU_VBIF_QOS_REMAP), 601 .xin_halt_timeout = 0x4000, 602 .qos_rp_remap_size = 0x40, 603 .qos_rt_tbl = { 604 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 605 .priority_lvl = sdm845_rt_pri_lvl, 606 }, 607 .qos_nrt_tbl = { 608 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 609 .priority_lvl = sdm845_nrt_pri_lvl, 610 }, 611 .memtype_count = 16, 612 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 613 }, 614 }; 615 616 static const struct dpu_vbif_cfg sm8650_vbif[] = { 617 { 618 .name = "vbif_rt", .id = VBIF_RT, 619 .base = 0, .len = 0x1074, 620 .features = BIT(DPU_VBIF_QOS_REMAP), 621 .xin_halt_timeout = 0x4000, 622 .qos_rp_remap_size = 0x40, 623 .qos_rt_tbl = { 624 .npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl), 625 .priority_lvl = sm8650_rt_pri_lvl, 626 }, 627 .qos_nrt_tbl = { 628 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 629 .priority_lvl = sdm845_nrt_pri_lvl, 630 }, 631 .memtype_count = 16, 632 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 633 }, 634 }; 635 636 /************************************************************* 637 * PERF data config 638 *************************************************************/ 639 640 /* SSPP QOS LUTs */ 641 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 642 {.fl = 4, .lut = 0x1b}, 643 {.fl = 5, .lut = 0x5b}, 644 {.fl = 6, .lut = 0x15b}, 645 {.fl = 7, .lut = 0x55b}, 646 {.fl = 8, .lut = 0x155b}, 647 {.fl = 9, .lut = 0x555b}, 648 {.fl = 10, .lut = 0x1555b}, 649 {.fl = 11, .lut = 0x5555b}, 650 {.fl = 12, .lut = 0x15555b}, 651 {.fl = 0, .lut = 0x55555b} 652 }; 653 654 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 655 {.fl = 4, .lut = 0x357}, 656 {.fl = 5, .lut = 0x3357}, 657 {.fl = 6, .lut = 0x23357}, 658 {.fl = 7, .lut = 0x223357}, 659 {.fl = 8, .lut = 0x2223357}, 660 {.fl = 9, .lut = 0x22223357}, 661 {.fl = 10, .lut = 0x222223357}, 662 {.fl = 11, .lut = 0x2222223357}, 663 {.fl = 12, .lut = 0x22222223357}, 664 {.fl = 13, .lut = 0x222222223357}, 665 {.fl = 14, .lut = 0x1222222223357}, 666 {.fl = 0, .lut = 0x11222222223357} 667 }; 668 669 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 670 {.fl = 10, .lut = 0x1aaff}, 671 {.fl = 11, .lut = 0x5aaff}, 672 {.fl = 12, .lut = 0x15aaff}, 673 {.fl = 0, .lut = 0x55aaff}, 674 }; 675 676 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 677 {.fl = 0, .lut = 0x0011222222335777}, 678 }; 679 680 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { 681 {.fl = 0, .lut = 0x0011223445566777 }, 682 }; 683 684 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 685 {.fl = 0, .lut = 0x0011222222223357 }, 686 }; 687 688 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 689 {.fl = 4, .lut = 0x0000000000000357 }, 690 }; 691 692 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 693 {.fl = 0, .lut = 0x0011222222335777}, 694 }; 695 696 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 697 {.fl = 10, .lut = 0x344556677}, 698 {.fl = 11, .lut = 0x3344556677}, 699 {.fl = 12, .lut = 0x23344556677}, 700 {.fl = 13, .lut = 0x223344556677}, 701 {.fl = 14, .lut = 0x1223344556677}, 702 {.fl = 0, .lut = 0x112233344556677}, 703 }; 704 705 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 706 {.fl = 0, .lut = 0x0011223344556677}, 707 }; 708 709 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 710 {.fl = 10, .lut = 0x0000000344556677}, 711 }; 712 713 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 714 {.fl = 0, .lut = 0x0}, 715 }; 716 717 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 718 {.fl = 0, .lut = 0x0}, 719 }; 720 721 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 722 {.fl = 0, .lut = 0x0}, 723 }; 724 725 /************************************************************* 726 * Hardware catalog 727 *************************************************************/ 728 729 #include "catalog/dpu_1_7_msm8996.h" 730 #include "catalog/dpu_1_14_msm8937.h" 731 #include "catalog/dpu_1_15_msm8917.h" 732 #include "catalog/dpu_1_16_msm8953.h" 733 734 #include "catalog/dpu_3_0_msm8998.h" 735 #include "catalog/dpu_3_2_sdm660.h" 736 #include "catalog/dpu_3_3_sdm630.h" 737 738 #include "catalog/dpu_4_0_sdm845.h" 739 #include "catalog/dpu_4_1_sdm670.h" 740 741 #include "catalog/dpu_5_0_sm8150.h" 742 #include "catalog/dpu_5_1_sc8180x.h" 743 #include "catalog/dpu_5_2_sm7150.h" 744 #include "catalog/dpu_5_3_sm6150.h" 745 #include "catalog/dpu_5_4_sm6125.h" 746 747 #include "catalog/dpu_6_0_sm8250.h" 748 #include "catalog/dpu_6_2_sc7180.h" 749 #include "catalog/dpu_6_3_sm6115.h" 750 #include "catalog/dpu_6_4_sm6350.h" 751 #include "catalog/dpu_6_5_qcm2290.h" 752 #include "catalog/dpu_6_9_sm6375.h" 753 754 #include "catalog/dpu_7_0_sm8350.h" 755 #include "catalog/dpu_7_2_sc7280.h" 756 757 #include "catalog/dpu_8_0_sc8280xp.h" 758 #include "catalog/dpu_8_1_sm8450.h" 759 #include "catalog/dpu_8_4_sa8775p.h" 760 761 #include "catalog/dpu_9_0_sm8550.h" 762 763 #include "catalog/dpu_9_2_x1e80100.h" 764 765 #include "catalog/dpu_10_0_sm8650.h" 766