Home
last modified time | relevance | path

Searched +full:0 +full:x1020 (Results 1 – 25 of 115) sorted by relevance

12345

/linux-5.10/include/linux/mtd/
Ddoc2000.h17 #define DoC_Sig1 0
20 #define DoC_ChipID 0x1000
21 #define DoC_DOCStatus 0x1001
22 #define DoC_DOCControl 0x1002
23 #define DoC_FloorSelect 0x1003
24 #define DoC_CDSNControl 0x1004
25 #define DoC_CDSNDeviceSelect 0x1005
26 #define DoC_ECCConf 0x1006
27 #define DoC_2k_ECCStatus 0x1007
29 #define DoC_CDSNSlowIO 0x100d
[all …]
/linux-5.10/drivers/media/dvb-frontends/
Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/linux-5.10/drivers/mmc/host/
Dsdhci-pci-dwc-mshc.c15 #define SDHCI_VENDOR_PTR_R 0xE8
18 #define SDHC_GPIO_OUT 0x34
19 #define SDHC_AT_CTRL_R 0x40
20 #define SDHC_SW_TUNE_EN 0x00000010
23 #define SDHC_MMCM_DIV_REG 0x1020
24 #define DIV_REG_100_MHZ 0x1145
25 #define DIV_REG_200_MHZ 0x1083
26 #define SDHC_MMCM_CLKFBOUT 0x1024
27 #define CLKFBOUT_100_MHZ 0x0000
28 #define CLKFBOUT_200_MHZ 0x0080
[all …]
/linux-5.10/arch/powerpc/kernel/
Dhead_40x.S82 . = 0xc0
104 stw r10,crit_r10@l(0); /* save two registers to work with */\
105 stw r11,crit_r11@l(0); \
130 stw r1,0(r11); \
132 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
164 * 0x0100 - Critical Interrupt Exception
166 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
169 * 0x0200 - Machine Check Exception
171 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
174 * 0x0300 - Data Storage Exception
[all …]
/linux-5.10/drivers/clk/qcom/
Dgpucc-msm8998.c36 .halt_reg = 0x1020,
38 .enable_reg = 0x1020,
39 .enable_mask = BIT(0),
54 { 0x0, 1 },
55 { 0x1, 2 },
56 { 0x3, 4 },
57 { 0x7, 8 },
62 .offset = 0x0,
73 .offset = 0x0,
88 { P_XO, 0 },
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Dsprd,sc9863a-clk.yaml82 reg = <0x21500000 0x1000>;
91 reg = <0x20e00000 0x4000>;
94 ranges = <0 0x20e00000 0x4000>;
96 apahb_gate: apahb-gate@0 {
98 reg = <0x0 0x1020>;
/linux-5.10/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux-5.10/drivers/media/platform/qcom/venus/
Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 (VBIF_BASE + 0x208)
12 #define VBIF_AXI_HALT_CTRL1 (VBIF_BASE + 0x20c)
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
19 #define CPU_CS_BASE (CPU_BASE + 0x12000)
20 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE + 0x1c)
24 #define VIDC_CTRL_INIT (CPU_CS_BASE + 0x48)
[all …]
/linux-5.10/arch/sh/include/mach-common/mach/
Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/linux-5.10/drivers/gpu/drm/hisilicon/kirin/
Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x2/
Dusb_mac.c11 s8 offset = 0; in mt76x2u_mac_fixup_xtal()
16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal()
17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal()
18 offset = 0; in mt76x2u_mac_fixup_xtal()
19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal()
20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal()
23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal()
25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal()
27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal()
28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal()
[all …]
/linux-5.10/Documentation/devicetree/bindings/sound/
Dqcom,lpass-cpu.yaml66 const: 0
69 "^dai-link@[0-9a-f]$":
187 reg = <0 0x62d87000 0 0x68000>,
188 <0 0x62f00000 0 0x29000>;
191 iommus = <&apps_smmu 0x1020 0>,
192 <&apps_smmu 0x1032 0>;
193 power-domains = <&lpass_hm 0>;
206 interrupts = <0 160 1>,
207 <0 268 1>;
213 #size-cells = <0>;
[all …]
/linux-5.10/include/linux/soc/samsung/
Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux-5.10/drivers/gpu/drm/lima/
Dlima_regs.h14 #define LIMA_PMU_POWER_UP 0x00
15 #define LIMA_PMU_POWER_DOWN 0x04
16 #define LIMA_PMU_POWER_GP0_MASK BIT(0)
29 #define LIMA_PMU_STATUS 0x08
30 #define LIMA_PMU_INT_MASK 0x0C
31 #define LIMA_PMU_INT_RAWSTAT 0x10
32 #define LIMA_PMU_INT_CLEAR 0x18
33 #define LIMA_PMU_INT_CMD_MASK BIT(0)
34 #define LIMA_PMU_SW_DELAY 0x1C
37 #define LIMA_L2_CACHE_SIZE 0x0004
[all …]
/linux-5.10/arch/arm64/boot/dts/sprd/
Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
61 reg = <0 0x1100>;
69 reg = <0 0x40353000 0 0x3000>;
[all …]
/linux-5.10/arch/m68k/include/asm/
Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]
/linux-5.10/drivers/staging/emxx_udc/
Demxx_udc.h21 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */
22 #define INT_VBUS 0 /* IRQ for GPIO_P153 */
48 #define U2F_DISABLE 0
62 #define MAX_TEST_MODE_NUM 0x05
65 /*------- (0x0004) USB Status Register */
75 /*------- (0x0008) USB Address Register */
76 #define USB_ADDR 0x007F0000
79 #define FRAME 0x000007FF
83 /*------- (0x000C) UTMI Characteristic 1 Register */
88 /*------- (0x0010) TEST Control Register */
[all …]
/linux-5.10/arch/arm/boot/dts/
Dimx23-pinfunc.h19 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
20 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
21 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
22 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
23 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
24 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
25 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
26 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
27 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
28 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
Dimx6ul-ccimx6ulsbcpro.dts21 pwms = <&pwm5 0 50000>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
51 pinctrl-0 = <&pinctrl_adc1>;
57 pinctrl-0 = <&pinctrl_flexcan1>;
65 pinctrl-0 = <&pinctrl_flexcan2>;
73 pinctrl-0 = <&pinctrl_ecspi1_master>;
79 pinctrl-0 = <&pinctrl_enet1>;
87 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
96 #size-cells = <0>;
98 ethphy0: ethernet-phy@0 {
[all …]
/linux-5.10/drivers/net/fddi/skfp/h/
Dsmt_p.h19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
/linux-5.10/drivers/mtd/devices/
Ddocg3.h15 * - 0x0000 .. 0x07ff : IPL
16 * - 0x0800 .. 0x0fff : Data area
17 * - 0x1000 .. 0x17ff : Registers
18 * - 0x1800 .. 0x1fff : Unknown
20 #define DOC_IOSPACE_IPL 0x0000
21 #define DOC_IOSPACE_DATA 0x0800
22 #define DOC_IOSPACE_SIZE 0x2000
30 #define DOC_ADDR_PAGE_MASK 0x3f
48 #define DOC_ECC_BCH_PRIMPOLY 0x4443
59 #define DOC_LAYOUT_BLOCK_BBT 0
[all …]
/linux-5.10/drivers/net/usb/
Dpegasus.h9 #define PEGASUS_II 0x80000000
10 #define HAS_HOME_PNA 0x40000000
14 #define EPROM_WRITE 0x01
15 #define EPROM_READ 0x02
16 #define EPROM_DONE 0x04
17 #define EPROM_WR_ENABLE 0x10
18 #define EPROM_LOAD 0x20
20 #define PHY_DONE 0x80
21 #define PHY_READ 0x40
22 #define PHY_WRITE 0x20
[all …]
/linux-5.10/arch/powerpc/include/asm/
Dspu.h23 #define MFC_PUT_CMD 0x20
24 #define MFC_PUTS_CMD 0x28
25 #define MFC_PUTR_CMD 0x30
26 #define MFC_PUTF_CMD 0x22
27 #define MFC_PUTB_CMD 0x21
28 #define MFC_PUTFS_CMD 0x2A
29 #define MFC_PUTBS_CMD 0x29
30 #define MFC_PUTRF_CMD 0x32
31 #define MFC_PUTRB_CMD 0x31
32 #define MFC_PUTL_CMD 0x24
[all …]
/linux-5.10/drivers/phy/samsung/
Dphy-exynos-mipi-video.c64 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
67 .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
73 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
76 .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
109 .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
112 .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
118 .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
121 .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
154 #define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
155 #define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
[all …]
/linux-5.10/drivers/net/wireless/ti/wlcore/
Devent.c19 #define WL18XX_LOGGER_SDIO_BUFF_MAX (0x1020)
20 #define WL18XX_DATA_RAM_BASE_ADDRESS (0x20000000)
21 #define WL18XX_LOGGER_SDIO_BUFF_ADDR (0x40159c)
43 fw_log.actual_buff_size = cpu_to_le32(0); in wlcore_event_fw_logger()
49 if (ret < 0) { in wlcore_event_fw_logger()
52 fw_log.actual_buff_size = cpu_to_le32(0); in wlcore_event_fw_logger()
58 if (le32_to_cpu(fw_log.actual_buff_size) == 0) in wlcore_event_fw_logger()
105 s8 metric = metric_arr[0]; in wlcore_event_rssi_trigger()
169 wl1271_debug(DEBUG_EVENT, "PERIODIC_SCAN_COMPLETE_EVENT (status 0x%0x)", in wlcore_event_sched_scan_completed()
185 wl1271_debug(DEBUG_EVENT, "%s: roles=0x%lx allowed=0x%lx", in wlcore_event_ba_rx_constraint()
[all …]

12345