powerpc/kernel/head_40x.S

82 	. = 0xc0
104 	stw	r10,crit_r10@l(0);	/* save two registers to work with */\
105 	stw	r11,crit_r11@l(0);					     \
130 	stw	r1,0(r11);						     \
132 	rlwinm	r9,r9,0,14,12;		/* clear MSR_WE (necessary?)	   */\
164  * 0x0100 - Critical Interrupt Exception
166 	CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
169  * 0x0200 - Machine Check Exception
171 	CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
174  * 0x0300 - Data Storage Exception
180 	START_EXCEPTION(0x0300,	DataStorage)
186 	EXC_XFER_LITE(0x300, handle_page_fault)
189  * 0x0400 - Instruction Storage Exception
192 	START_EXCEPTION(0x0400, InstructionAccess)
196 	li	r5,0			/* Pass zero as arg3 */
197 	EXC_XFER_LITE(0x400, handle_page_fault)
199 /* 0x0500 - External Interrupt Exception */
200 	EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
202 /* 0x0600 - Alignment Exception */
203 	START_EXCEPTION(0x0600, Alignment)
208 	EXC_XFER_STD(0x600, alignment_exception)
210 /* 0x0700 - Program Exception */
211 	START_EXCEPTION(0x0700, ProgramCheck)
216 	EXC_XFER_STD(0x700, program_check_exception)
218 	EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_STD)
219 	EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_STD)
220 	EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_STD)
221 	EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_STD)
223 /* 0x0C00 - System Call Exception */
224 	START_EXCEPTION(0x0C00,	SystemCall)
225 	SYSCALL_ENTRY	0xc00
228 /*	EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_STD) */
229 	EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_STD)
230 	EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD)
232 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
233 	. = 0x1000
236 /* 0x1010 - Fixed Interval Timer (FIT) Exception
238 	. = 0x1010
241 /* 0x1020 - Watchdog Timer (WDT) Exception
243 	. = 0x1020
246 /* 0x1100 - Data TLB Miss Exception
251 	START_EXCEPTION(0x1100,	DTLBMiss)
269 	li	r9, 0
270 	mtspr	SPRN_PID, r9		/* TLB will have 0 TID */
281 	lwz	r11, 0(r11)		/* Get L1 entry */
286 	lwz	r11, 0(r11)		/* Get Linux PTE */
293 	rlwimi	r11, r9, 0, _PAGE_RW	/* replace rw by hwwrite */
298 	li	r9, 0x00c0
299 	rlwimi	r10, r9, 0, 20, 31
310 	ori	r9, r9, 0x40
311 	rlwimi	r10, r9, 0, 20, 31
328 /* 0x1200 - Instruction TLB Miss Exception
332 	START_EXCEPTION(0x1200,	ITLBMiss)
350 	li	r9, 0
351 	mtspr	SPRN_PID, r9		/* TLB will have 0 TID */
362 	lwz	r11, 0(r11)		/* Get L1 entry */
367 	lwz	r11, 0(r11)		/* Get Linux PTE */
374 	rlwimi	r11, r9, 0, _PAGE_RW	/* replace rw by hwwrite */
379 	li	r9, 0x00c0
380 	rlwimi	r10, r9, 0, 20, 31
391 	ori	r9, r9, 0x40
392 	rlwimi	r10, r9, 0, 20, 31
409 	EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD)
410 	EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_STD)
411 	EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
412 	EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD)
413 	EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD)
414 	EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
415 	EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
416 	EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_STD)
417 	EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_STD)
418 	EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_STD)
419 	EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_STD)
420 	EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_STD)
421 	EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_STD)
436 	/* 0x2000 - Debug Exception */
437 	START_EXCEPTION(0x2000, DebugTrap)
456 	cmplwi  r10,0x2100
460 1:	rlwinm	r9,r9,0,~MSR_DE		/* clear DE in the SRR3 value */
467 	mtcrf	0x80,r10
472 	lwz	r10,crit_r10@l(0)
473 	lwz	r11,crit_r11@l(0)
480 	EXC_XFER_TEMPLATE(DebugException, 0x2002, \
484 	/* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
490 	EXC_XFER_LITE(0x1000, timer_interrupt)
492 	/* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
496 	EXC_XFER_STD(0x1010, unknown_exception)
498 	/* Watchdog Timer (WDT) Exception. (from 0x1020) */
502 	EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2,
507  * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
524 	.long	0
531 	li	r9, 0x0ce2
535 	lwz	r9, tlb_4xx_index@l(0)
538 	stw	r9, tlb_4xx_index@l(0)
571 	li	r0,0
582 	li	r3,0
614 	stw	r5, 0xf0(0)	/* Must match your Abatron config file */
616 	stw	r6, 0(r5)
636 	/* We should still be executing code at physical address 0x0000xxxx
638 	 * 0xC000xxxx. So, set up a TLB mapping to cover this once
650 	li	r0,0
688 	stw	r4, abatron_pteptrs@l + 0x4(r5)