Lines Matching +full:0 +full:x1020
36 .halt_reg = 0x1020,
38 .enable_reg = 0x1020,
39 .enable_mask = BIT(0),
54 { 0x0, 1 },
55 { 0x1, 2 },
56 { 0x3, 4 },
57 { 0x7, 8 },
62 .offset = 0x0,
73 .offset = 0x0,
88 { P_XO, 0 },
98 { P_XO, 0 },
108 F(19200000, P_XO, 1, 0, 0),
109 F(50000000, P_GPLL0, 12, 0, 0),
114 .cmd_rcgr = 0x1030,
132 .cmd_rcgr = 0x1070,
146 F(19200000, P_XO, 1, 0, 0),
151 .cmd_rcgr = 0x10b0,
164 F(19200000, P_XO, 1, 0, 0),
165 F(40000000, P_GPLL0, 15, 0, 0),
166 F(200000000, P_GPLL0, 3, 0, 0),
167 F(300000000, P_GPLL0, 2, 0, 0),
172 .cmd_rcgr = 0x1100,
185 .halt_reg = 0x1054,
187 .enable_reg = 0x1054,
188 .enable_mask = BIT(0),
200 .halt_reg = 0x1098,
202 .enable_reg = 0x1098,
203 .enable_mask = BIT(0),
215 .halt_reg = 0x10d0,
217 .enable_reg = 0x10d0,
218 .enable_mask = BIT(0),
230 .halt_reg = 0x1124,
232 .enable_reg = 0x1124,
233 .enable_mask = BIT(0),
244 .gdscr = 0x1004,
245 .gds_hw_ctrl = 0x1008,
254 .gdscr = 0x1094,
255 .clamp_io_ctrl = 0x130,
284 [GPU_CX_BCR] = { 0x1000 },
285 [RBCPR_BCR] = { 0x1050 },
286 [GPU_GX_BCR] = { 0x1090 },
287 [GPU_ISENSE_BCR] = { 0x1120 },
294 .max_register = 0x9000,
325 regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0)); in gpucc_msm8998_probe()