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/qemu/hw/net/
H A Digb_regs.h14 #define E1000_DEV_ID_82576 0x10C9
15 #define E1000_DEV_ID_82576_FIBER 0x10E6
16 #define E1000_DEV_ID_82576_SERDES 0x10E7
17 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
18 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
19 #define E1000_DEV_ID_82576_NS 0x150A
20 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
21 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
45 #define E1000_ADVTXD_POTS_IXSM 0x00000100 /* Insert TCP/UDP Checksum */
46 #define E1000_ADVTXD_POTS_TXSM 0x00000200 /* Insert TCP/UDP Checksum */
[all …]
/qemu/include/hw/arm/
H A Dfsl-imx6ul.h97 FSL_IMX6UL_MMDC_ADDR = 0x80000000,
100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
116 FSL_IMX6UL_UART6_ADDR = 0x021FC000,
118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
120 FSL_IMX6UL_UART5_ADDR = 0x021F4000,
121 FSL_IMX6UL_UART4_ADDR = 0x021F0000,
[all …]
/qemu/include/hw/ppc/
H A Dpnv_xscom.h43 * GPIO 0x1100xxxx
44 * SCOM 0x1101xxxx
45 * OHA 0x1102xxxx
46 * CLOCK CTL 0x1103xxxx
47 * FIR 0x1104xxxx
48 * THERM 0x1105xxxx
49 * <reserved> 0x1106xxxx
51 * 0x110Exxxx
52 * PCB SLAVE 0x110Fxxxx
55 #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
[all …]
H A Dpnv_xive.h24 #define XIVE_TABLE_BLK_MAX 16 /* Block Scope Table (0-15) */
26 #define XIVE_TABLE_VDT_MAX 16 /* VDT Domain Table (0-15) */
27 #define XIVE_TABLE_EDT_MAX 64 /* EDT Domain Table (0-63) */
75 uint64_t regs[0x300];
136 uint64_t cq_regs[0x40];
137 uint64_t vc_regs[0x100];
138 uint64_t pc_regs[0x100];
139 uint64_t tctxt_regs[0x30];
/qemu/include/hw/net/
H A Dftgmac100.h17 #define FTGMAC100_MEM_SIZE 0x1000
18 #define FTGMAC100_REG_MEM_SIZE 0x100
19 #define FTGMAC100_REG_HIGH_MEM_SIZE 0x100
20 #define FTGMAC100_REG_HIGH_OFFSET 0x100
/qemu/hw/audio/
H A Dgusemu_mixer.c45 for (count = 0; count < numsamples * 2; count++) in gus_mixvoices()
46 *(bufferpos + count) = 0; /* clear */ in gus_mixvoices()
50 if (!(GUSregb(GUS4cReset) & 0x01)) /* reset flag active? */ in gus_mixvoices()
53 for (Voice = 0; Voice <= (GUSregb(NumVoices) & 31); Voice++) in gus_mixvoices()
55 if (GUSvoice(wVSRControl) & 0x200) in gus_mixvoices()
56 GUSvoice(wVSRControl) |= 0x100; /* voice stop request */ in gus_mixvoices()
57 if (GUSvoice(wVSRVolRampControl) & 0x200) in gus_mixvoices()
58 GUSvoice(wVSRVolRampControl) |= 0x100; /* Volume ramp stop request */ in gus_mixvoices()
59 …if (!(GUSvoice(wVSRControl) & GUSvoice(wVSRVolRampControl) & 0x100)) /* neither voice nor volume c… in gus_mixvoices()
69 int PanningPos = (GUSvoice(wVSRPanning) >> 8) & 0xf; in gus_mixvoices()
[all …]
/qemu/tests/tcg/openrisc/
H A Dtest_sub.c8 a = 0x100; in main()
9 b = 0x100; in main()
10 result = 0x0; in main()
12 ("l.sub %0, %0, %1\n\t" in main()
21 a = 0xffff; in main()
22 b = 0x1; in main()
23 result = 0xfffe; in main()
25 ("l.sub %0, %0, %1\n\t" in main()
34 return 0; in main()
H A Dtest_add.c8 a = 0x100; in main()
9 b = 0x100; in main()
10 result = 0x200; in main()
12 ("l.add %0, %0, %1\n\t" in main()
21 a = 0xffff; in main()
22 b = 0x1; in main()
23 result = 0x10000; in main()
25 ("l.add %0, %0, %1\n\t" in main()
34 a = 0x7fffffff; in main()
35 b = 0x1; in main()
[all …]
H A Dtest_addic.c9 result = 0x0; in main()
12 "l.addic %0, %0, 0xffff\n\t" in main()
21 result = 0x201; in main()
24 "l.addic %0, %0, 0x1\n\t" in main()
25 "l.ori %0, r0, 0x100\n\t" in main()
26 "l.addic %0, %0, 0x100\n\t" in main()
34 return 0; in main()
/qemu/hw/cpu/
H A Darm11mpcore.c36 memory_region_add_subregion(&s->container, 0, in mpcore_priv_map_setup()
37 sysbus_mmio_get_region(scubusdev, 0)); in mpcore_priv_map_setup()
38 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs in mpcore_priv_map_setup()
39 * at 0x200, 0x300... in mpcore_priv_map_setup()
41 for (i = 0; i < (s->num_cpu + 1); i++) { in mpcore_priv_map_setup()
42 hwaddr offset = 0x100 + (i * 0x100); in mpcore_priv_map_setup()
49 for (i = 0; i < (s->num_cpu + 1); i++) { in mpcore_priv_map_setup()
50 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ in mpcore_priv_map_setup()
51 hwaddr offset = 0x600 + i * 0x100; in mpcore_priv_map_setup()
54 memory_region_add_subregion(&s->container, offset + 0x20, in mpcore_priv_map_setup()
[all …]
/qemu/hw/dma/
H A Dxlnx_dpdma.c34 #define DEBUG_DPDMA 0
41 } while (0)
46 #define DPDMA_ERR_CTRL (0x0000)
47 #define DPDMA_ISR (0x0004 >> 2)
48 #define DPDMA_IMR (0x0008 >> 2)
49 #define DPDMA_IEN (0x000C >> 2)
50 #define DPDMA_IDS (0x0010 >> 2)
51 #define DPDMA_EISR (0x0014 >> 2)
52 #define DPDMA_EIMR (0x0018 >> 2)
53 #define DPDMA_EIEN (0x001C >> 2)
[all …]
/qemu/include/hw/pci-host/
H A Dls7a.h16 #define VIRT_PCI_MEM_BASE 0x40000000UL
17 #define VIRT_PCI_MEM_SIZE 0x40000000UL
18 #define VIRT_PCI_IO_OFFSET 0x4000
19 #define VIRT_PCI_CFG_BASE 0x20000000
20 #define VIRT_PCI_CFG_SIZE 0x08000000
21 #define VIRT_PCI_IO_BASE 0x18004000UL
22 #define VIRT_PCI_IO_SIZE 0xC000
24 #define VIRT_PCH_REG_BASE 0x10000000UL
26 #define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
27 #define VIRT_PCH_REG_SIZE 0x400
[all …]
/qemu/tests/unit/
H A Dtest-logging.c38 qemu_set_dfilter_ranges("0x1000+0x100", &error_abort); in test_parse_range()
40 g_assert_false(qemu_log_in_addr_range(0xfff)); in test_parse_range()
41 g_assert(qemu_log_in_addr_range(0x1000)); in test_parse_range()
42 g_assert(qemu_log_in_addr_range(0x1001)); in test_parse_range()
43 g_assert(qemu_log_in_addr_range(0x10ff)); in test_parse_range()
44 g_assert_false(qemu_log_in_addr_range(0x1100)); in test_parse_range()
46 qemu_set_dfilter_ranges("0x1000-0x100", &error_abort); in test_parse_range()
48 g_assert_false(qemu_log_in_addr_range(0x1001)); in test_parse_range()
49 g_assert(qemu_log_in_addr_range(0x1000)); in test_parse_range()
50 g_assert(qemu_log_in_addr_range(0x0f01)); in test_parse_range()
[all …]
/qemu/include/hw/intc/
H A Dloongarch_pic_common.h13 #define PCH_PIC_INT_ID 0x00
14 #define PCH_PIC_INT_ID_VAL 0x7
15 #define PCH_PIC_INT_ID_VER 0x1
16 #define PCH_PIC_INT_MASK 0x20
17 #define PCH_PIC_HTMSI_EN 0x40
18 #define PCH_PIC_INT_EDGE 0x60
19 #define PCH_PIC_INT_CLEAR 0x80
20 #define PCH_PIC_AUTO_CTRL0 0xc0
21 #define PCH_PIC_AUTO_CTRL1 0xe0
22 #define PCH_PIC_ROUTE_ENTRY 0x100
[all …]
/qemu/hw/intc/
H A Dpl190.c48 { 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };
61 set = (level & s->prio_mask[s->priority]) != 0; in pl190_update()
63 set = ((s->level | s->soft_level) & s->fiq_select) != 0; in pl190_update()
84 mask = 0; in pl190_update_vectors()
85 for (i = 0; i < 16; i++) in pl190_update_vectors()
88 if (s->vect_control[i] & 0x20) in pl190_update_vectors()
90 n = s->vect_control[i] & 0x1f; in pl190_update_vectors()
104 if (offset >= 0xfe0 && offset < 0x1000) { in pl190_read()
105 return pl190_id[(offset - 0xfe0) >> 2]; in pl190_read()
107 if (offset >= 0x100 && offset < 0x140) { in pl190_read()
[all …]
/qemu/target/avr/
H A Dgdbstub.c43 return gdb_get_reg16(mem_buf, env->sp & 0x0000ffff); in avr_cpu_gdb_read_register()
51 return 0; in avr_cpu_gdb_read_register()
82 return 0; in avr_cpu_gdb_write_register()
89 * Let's assume main has address 0x100: in avr_cpu_gdb_adjust_breakpoint()
90 * b main - sets breakpoint at address 0x00000100 (code) in avr_cpu_gdb_adjust_breakpoint()
91 * b *0x100 - sets breakpoint at address 0x00800100 (data) in avr_cpu_gdb_adjust_breakpoint()
/qemu/hw/riscv/
H A Dopentitan.c42 [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
43 [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
44 [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
45 [IBEX_DEV_UART] = { 0x40000000, 0x40 },
46 [IBEX_DEV_GPIO] = { 0x40040000, 0x40 },
47 [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 },
48 [IBEX_DEV_I2C] = { 0x40080000, 0x80 },
49 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 },
50 [IBEX_DEV_TIMER] = { 0x40100000, 0x200 },
51 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 },
[all …]
/qemu/pc-bios/s390-ccw/
H A Ds390-arch.h28 #define PSW_MASK_IOINT 0x0200000000000000ULL
29 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
30 #define PSW_MASK_WAIT 0x0002000000000000ULL
31 #define PSW_MASK_EAMODE 0x0000000100000000ULL
32 #define PSW_MASK_BAMODE 0x0000000080000000ULL
33 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
39 PSWLegacy ipl_psw; /* 0x000 */
40 uint32_t ccw1[2]; /* 0x008 */
42 uint32_t ccw2[2]; /* 0x010 */
48 uint8_t pad1[0x80 - 0x18]; /* 0x018 */
[all …]
/qemu/tests/qtest/
H A Dpnv-spi-seeprom-test.c16 #define SPIC2_XSCOM_BASE 0xc0040
19 #define READ_OP_TDR_DATA 0x0300010000000000
24 #define READ_OP_COUNTER_CONFIG 0x2040000000002b00
26 #define READ_OP_SEQUENCER 0x1130404040404010
29 #define WRITE_OP_WREN 0x0600000000000000
31 #define WRITE_OP_TDR_DATA 0x0300010012345678
33 #define WRITE_OP_COUNTER_CONFIG 0x4000000000002000
35 #define WRITE_OP_SEQUENCER 0x1130100000000000
57 pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, 0); in spi_seeprom_transaction()
58 /* Read 5*8 bytes from SEEPROM at 0x100 */ in spi_seeprom_transaction()
[all …]
/qemu/docs/
H A Dpcie_sriov.txt37 supports functions beyond it's "own" function space (0-7),
49 int ret = pcie_endpoint_cap_init(d, 0x70);
51 pcie_ari_init(d, 0x100);
55 if (!pcie_sriov_pf_init(d, 0x200, "your_virtual_dev",
81 int ret = pcie_endpoint_cap_init(d, 0x60);
83 pcie_ari_init(d, 0x100);
105 echo 0 > /sys/bus/pci/devices/0000:01:00.0/sriov_numvfs
/qemu/hw/usb/
H A Dchipidea.c18 CHIPIDEA_USBx_DCIVERSION = 0x000,
19 CHIPIDEA_USBx_DCCPARAMS = 0x004,
26 return 0; in chipidea_read()
56 return 0x1; in chipidea_dc_read()
67 return 0; in chipidea_dc_read()
98 for (i = 0; i < ARRAY_SIZE(ci->iomem); i++) { in chipidea_init()
106 * Registers located between offsets 0x000 and 0xFC in chipidea_init()
110 .offset = 0x000, in chipidea_init()
111 .size = 0x100, in chipidea_init()
115 * Registers located between offsets 0x1A4 and 0x1DC in chipidea_init()
[all …]
/qemu/linux-user/riscv/
H A Dvdso-asmoffset.h2 # define sizeof_rt_sigframe 0x2b0
3 # define offsetof_uc_mcontext 0x120
4 # define offsetof_freg0 0x80
6 # define sizeof_rt_sigframe 0x340
7 # define offsetof_uc_mcontext 0x130
8 # define offsetof_freg0 0x100
/qemu/hw/misc/
H A Darm_l2x0.c30 #define CACHE_ID 0x410000c8
69 offset &= 0xfff; in l2x0_priv_read()
70 if (offset >= 0x730 && offset < 0x800) { in l2x0_priv_read()
71 return 0; /* cache ops complete */ in l2x0_priv_read()
74 case 0: in l2x0_priv_read()
76 case 0x4: in l2x0_priv_read()
81 case 0x100: in l2x0_priv_read()
83 case 0x104: in l2x0_priv_read()
85 case 0x108: in l2x0_priv_read()
87 case 0x10C: in l2x0_priv_read()
[all …]
/qemu/target/rx/
H A Dhelper.c28 if (env->psw_pm == 0) { in rx_cpu_unpack_psw()
50 env->in_sleep = 0; in rx_cpu_do_interrupt()
53 env->usp = env->regs[0]; in rx_cpu_do_interrupt()
55 env->isp = env->regs[0]; in rx_cpu_do_interrupt()
58 env->psw_pm = env->psw_i = env->psw_u = 0; in rx_cpu_do_interrupt()
79 "interrupt 0x%02x raised\n", env->ack_irq); in rx_cpu_do_interrupt()
90 if (vec < 0x100) { in rx_cpu_do_interrupt()
91 env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4); in rx_cpu_do_interrupt()
93 env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4); in rx_cpu_do_interrupt()
111 case 0x100 ... 0x1ff: in rx_cpu_do_interrupt()
[all …]
/qemu/linux-headers/asm-loongarch/
H A Dkvm_para.h8 * CPUCFG index area: 0x40000000 -- 0x400000ff
11 #define CPUCFG_KVM_BASE 0x40000000
12 #define CPUCFG_KVM_SIZE 0x100
13 #define CPUCFG_KVM_SIG (CPUCFG_KVM_BASE + 0)
14 #define KVM_SIGNATURE "KVM\0"

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