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/linux-5.10/drivers/media/pci/cx18/
Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
[all …]
/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dtable.c7 0x01c, 0x07000000,
8 0x800, 0x00040000,
9 0x804, 0x00008003,
10 0x808, 0x0000fc00,
11 0x80c, 0x0000000a,
12 0x810, 0x10005088,
13 0x814, 0x020c3d10,
14 0x818, 0x00200185,
15 0x81c, 0x00000000,
16 0x820, 0x01000000,
[all …]
/linux-5.10/include/linux/
Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dsorg94.c33 nvkm_mask(device, 0x61c128 + loff, 0x0000003f, watermark); in g94_sor_dp_watermark()
42 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, TU << 2); in g94_sor_dp_activesym()
43 nvkm_mask(device, 0x61c128 + loff, 0x010f7f00, VTUa << 24 | in g94_sor_dp_activesym()
53 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h); in g94_sor_dp_audio_sym()
54 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v); in g94_sor_dp_audio_sym()
65 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive()
66 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive()
67 data[2] = nvkm_rd32(device, 0x61c130 + loff); in g94_sor_dp_drive()
68 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in g94_sor_dp_drive()
69 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in g94_sor_dp_drive()
[all …]
/linux-5.10/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_err.h15 #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
16 #define HCLGE_RAS_REG_NFE_MASK 0xFF00
17 #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
19 #define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
21 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
22 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
23 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
24 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
25 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
26 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
[all …]
/linux-5.10/drivers/net/wireless/ralink/rt2x00/
Drt2800.h49 #define RF2820 0x0001
50 #define RF2850 0x0002
51 #define RF2720 0x0003
52 #define RF2750 0x0004
53 #define RF3020 0x0005
54 #define RF2020 0x0006
55 #define RF3021 0x0007
56 #define RF3022 0x0008
57 #define RF3052 0x0009
58 #define RF2853 0x000a
[all …]
/linux-5.10/sound/soc/fsl/
Dfsl_dma.h10 u8 res0[0x100];
30 u8 res2[0x38];
35 #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
37 #define CCSR_DMA_MR_BWC_MASK 0x0F000000
40 #define CCSR_DMA_MR_EMP_EN 0x00200000
41 #define CCSR_DMA_MR_EMS_EN 0x00040000
42 #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
43 #define CCSR_DMA_MR_DAHTS_1 0x00000000
44 #define CCSR_DMA_MR_DAHTS_2 0x00010000
45 #define CCSR_DMA_MR_DAHTS_4 0x00020000
[all …]
/linux-5.10/drivers/staging/rtl8723bs/hal/
DHalHWImg8723B_MAC.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
41 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n", in CheckPositive()
51 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n", in CheckPositive()
62 " (Platform, Interface) = (0x%X, 0x%X)\n", in CheckPositive()
72 " (Board, Package) = (0x%X, 0x%X)\n", in CheckPositive()
82 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
84 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
90 cond1 &= 0x000F0FFF; in CheckPositive()
91 driver1 &= 0x000F0FFF; in CheckPositive()
[all …]
DHalHWImg8723B_BB.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
41 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n", in CheckPositive()
51 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n", in CheckPositive()
61 (" (Platform, Interface) = (0x%X, 0x%X)\n", in CheckPositive()
71 " (Board, Package) = (0x%X, 0x%X)\n", in CheckPositive()
81 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
83 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
89 cond1 &= 0x000F0FFF; in CheckPositive()
90 driver1 &= 0x000F0FFF; in CheckPositive()
[all …]
/linux-5.10/drivers/bus/
Dda8xx-mstpri.c29 #define DA8XX_MSTPRI0_OFFSET 0
34 DA8XX_MSTPRI_ARM_I = 0,
62 .shift = 0,
63 .mask = 0x0000000f,
68 .mask = 0x000000f0,
73 .mask = 0x000f0000,
78 .mask = 0x00f00000,
82 .shift = 0,
83 .mask = 0x0000000f,
88 .mask = 0x000000f0,
[all …]
/linux-5.10/drivers/atm/
DuPD98401.h14 #define uPD98401_PORTS 0x24 /* probably more ? */
21 #define uPD98401_OPEN_CHAN 0x20000000 /* open channel */
22 #define uPD98401_CHAN_ADDR 0x0003fff8 /* channel address */
24 #define uPD98401_CLOSE_CHAN 0x24000000 /* close channel */
25 #define uPD98401_CHAN_RT 0x02000000 /* RX/TX (0 TX, 1 RX) */
26 #define uPD98401_DEACT_CHAN 0x28000000 /* deactivate channel */
27 #define uPD98401_TX_READY 0x30000000 /* TX ready */
28 #define uPD98401_ADD_BAT 0x34000000 /* add batches */
29 #define uPD98401_POOL 0x000f0000 /* pool number */
31 #define uPD98401_POOL_NUMBAT 0x0000ffff /* number of batches */
[all …]
/linux-5.10/arch/mips/include/asm/mach-db1x00/
Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/linux-5.10/arch/sh/configs/
Dsh7757lcr_defconfig17 CONFIG_MEMORY_START=0x40000000
18 CONFIG_MEMORY_SIZE=0x0f000000
/linux-5.10/drivers/vme/bridges/
Dvme_ca91cx42.h21 #define PCI_VENDOR_ID_TUNDRA 0x10e3
25 #define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000
72 #define CA91CX42_PCI_ID 0x000
73 #define CA91CX42_PCI_CSR 0x004
74 #define CA91CX42_PCI_CLASS 0x008
75 #define CA91CX42_PCI_MISC0 0x00C
76 #define CA91CX42_PCI_BS 0x010
77 #define CA91CX42_PCI_MISC1 0x03C
79 #define LSI0_CTL 0x0100
80 #define LSI0_BS 0x0104
[all …]
/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/linux-5.10/arch/mips/boot/dts/loongson/
Dloongson64c-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
23 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
25 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
29 reg = <0 0x3ff01400 0x64>;
38 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
39 <0x0f000000>, /* int1 */
40 <0x00000000>, /* int2 */
41 <0x00000000>; /* int3 */
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Ddcb.c32 u16 dcb = 0x0000; in dcb_table()
35 dcb = nvbios_rd16(bios, 0x36); in dcb_table()
43 if (*ver >= 0x42) { in dcb_table()
44 nvkm_warn(subdev, "DCB version 0x%02x unknown\n", *ver); in dcb_table()
45 return 0x0000; in dcb_table()
47 if (*ver >= 0x30) { in dcb_table()
48 if (nvbios_rd32(bios, dcb + 6) == 0x4edcbdcb) { in dcb_table()
55 if (*ver >= 0x20) { in dcb_table()
56 if (nvbios_rd32(bios, dcb + 4) == 0x4edcbdcb) { in dcb_table()
64 if (*ver >= 0x15) { in dcb_table()
[all …]
/linux-5.10/arch/sparc/include/uapi/asm/
Dpsrcompat.h8 #define PSR_CWP 0x0000001f /* current window pointer */
9 #define PSR_ET 0x00000020 /* enable traps field */
10 #define PSR_PS 0x00000040 /* previous privilege level */
11 #define PSR_S 0x00000080 /* current privilege level */
12 #define PSR_PIL 0x00000f00 /* processor interrupt level */
13 #define PSR_EF 0x00001000 /* enable floating point */
14 #define PSR_EC 0x00002000 /* enable co-processor */
15 #define PSR_SYSCALL 0x00004000 /* inside of a syscall */
16 #define PSR_LE 0x00008000 /* SuperSparcII little-endian */
17 #define PSR_ICC 0x00f00000 /* integer condition codes */
[all …]
Dpsr.h19 * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
22 #define PSR_CWP 0x0000001f /* current window pointer */
23 #define PSR_ET 0x00000020 /* enable traps field */
24 #define PSR_PS 0x00000040 /* previous privilege level */
25 #define PSR_S 0x00000080 /* current privilege level */
26 #define PSR_PIL 0x00000f00 /* processor interrupt level */
27 #define PSR_EF 0x00001000 /* enable floating point */
28 #define PSR_EC 0x00002000 /* enable co-processor */
29 #define PSR_SYSCALL 0x00004000 /* inside of a syscall */
30 #define PSR_LE 0x00008000 /* SuperSparcII little-endian */
[all …]
/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,liointc.yaml53 interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
54 and each bit in the cell refers to a child interrupt from 0 to 31.
76 reg = <0x3ff01400 0x64>;
85 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
86 <0x0f000000>, /* int1 */
87 <0x00000000>, /* int2 */
88 <0x00000000>; /* int3 */
/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dvce_v4_0.c44 #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
65 if (ring->me == 0) in vce_v4_0_ring_get_rptr()
66 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); in vce_v4_0_ring_get_rptr()
68 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); in vce_v4_0_ring_get_rptr()
70 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); in vce_v4_0_ring_get_rptr()
87 if (ring->me == 0) in vce_v4_0_ring_get_wptr()
88 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr()
90 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr()
92 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); in vce_v4_0_ring_get_wptr()
113 if (ring->me == 0) in vce_v4_0_ring_set_wptr()
[all …]
/linux-5.10/arch/powerpc/include/asm/nohash/
Dmmu-book3e.h9 #define BOOK3E_PAGESZ_1K 0
44 #define MAS0_TLBSEL_MASK 0x30000000
49 #define MAS0_ESEL_MASK 0x0FFF0000
52 #define MAS0_NV(x) ((x) & 0x00000FFF)
53 #define MAS0_HES 0x00004000
54 #define MAS0_WQ_ALLWAYS 0x00000000
55 #define MAS0_WQ_COND 0x00001000
56 #define MAS0_WQ_CLR_RSRV 0x00002000
58 #define MAS1_VALID 0x80000000
59 #define MAS1_IPROT 0x40000000
[all …]
/linux-5.10/drivers/media/usb/cx231xx/
Dcx231xx-reg.h17 #define SAV_ACTIVE_VIDEO_FIELD1 0x80
18 #define EAV_ACTIVE_VIDEO_FIELD1 0x90
20 #define SAV_ACTIVE_VIDEO_FIELD2 0xc0
21 #define EAV_ACTIVE_VIDEO_FIELD2 0xd0
23 #define SAV_VBLANK_FIELD1 0xa0
24 #define EAV_VBLANK_FIELD1 0xb0
26 #define SAV_VBLANK_FIELD2 0xe0
27 #define EAV_VBLANK_FIELD2 0xf0
29 #define SAV_VBI_FIELD1 0x20
30 #define EAV_VBI_FIELD1 0x30
[all …]
/linux-5.10/drivers/staging/rtl8192u/
Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
/linux-5.10/drivers/gpu/drm/msm/adreno/
Da6xx.xml.h52 TILE6_LINEAR = 0,
182 DEPTH6_NONE = 0,
281 PERF_CP_ALWAYS_COUNT = 0,
334 PERF_RBBM_ALWAYS_COUNT = 0,
351 PERF_PC_BUSY_CYCLES = 0,
396 PERF_VFD_BUSY_CYCLES = 0,
422 PERF_HLSQ_BUSY_CYCLES = 0,
446 PERF_VPC_BUSY_CYCLES = 0,
477 PERF_TSE_BUSY_CYCLES = 0,
500 PERF_RAS_BUSY_CYCLES = 0,
[all …]

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