52 	TILE6_LINEAR = 0,
182 	DEPTH6_NONE = 0,
281 	PERF_CP_ALWAYS_COUNT = 0,
334 	PERF_RBBM_ALWAYS_COUNT = 0,
351 	PERF_PC_BUSY_CYCLES = 0,
396 	PERF_VFD_BUSY_CYCLES = 0,
422 	PERF_HLSQ_BUSY_CYCLES = 0,
446 	PERF_VPC_BUSY_CYCLES = 0,
477 	PERF_TSE_BUSY_CYCLES = 0,
500 	PERF_RAS_BUSY_CYCLES = 0,
516 	PERF_UCHE_BUSY_CYCLES = 0,
559 	PERF_TP_BUSY_CYCLES = 0,
619 	PERF_SP_BUSY_CYCLES = 0,
707 	PERF_RB_BUSY_CYCLES = 0,
758 	PERF_VSC_BUSY_CYCLES = 0,
766 	PERF_CCU_BUSY_CYCLES = 0,
798 	PERF_LRZ_BUSY_CYCLES = 0,
829 	PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
879 	R2D_RAW = 0,
883 	A6XX_EARLY_Z = 0,
889 	ROTATE_0 = 0,
898 	TESS_EQUAL = 0,
904 	TESS_POINTS = 0,
911 	A6XX_TEX_NEAREST = 0,
918 	A6XX_TEX_REPEAT = 0,
926 	A6XX_TEX_ANISO_1 = 0,
934 	A6XX_REDUCTION_MODE_AVERAGE = 0,
940 	A6XX_TEX_X = 0,
949 	A6XX_TEX_1D = 0,
955 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE			0x00000001
956 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR			0x00000002
957 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW	0x00000040
958 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR			0x00000080
959 #define A6XX_RBBM_INT_0_MASK_CP_SW				0x00000100
960 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR			0x00000200
961 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS		0x00000400
962 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS		0x00000800
963 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS			0x00001000
964 #define A6XX_RBBM_INT_0_MASK_CP_IB2				0x00002000
965 #define A6XX_RBBM_INT_0_MASK_CP_IB1				0x00004000
966 #define A6XX_RBBM_INT_0_MASK_CP_RB				0x00008000
967 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS			0x00020000
968 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS			0x00040000
969 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS			0x00100000
970 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW		0x00400000
971 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT			0x00800000
972 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS			0x01000000
973 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR			0x02000000
974 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0			0x04000000
975 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1			0x08000000
976 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ			0x40000000
977 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG			0x80000000
978 #define A6XX_CP_INT_CP_OPCODE_ERROR				0x00000001
979 #define A6XX_CP_INT_CP_UCODE_ERROR				0x00000002
980 #define A6XX_CP_INT_CP_HW_FAULT_ERROR				0x00000004
981 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR		0x00000010
982 #define A6XX_CP_INT_CP_AHB_ERROR				0x00000020
983 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR				0x00000040
984 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR			0x00000080
985 #define REG_A6XX_CP_RB_BASE					0x00000800
987 #define REG_A6XX_CP_RB_BASE_HI					0x00000801
989 #define REG_A6XX_CP_RB_CNTL					0x00000802
991 #define REG_A6XX_CP_RB_RPTR_ADDR_LO				0x00000804
993 #define REG_A6XX_CP_RB_RPTR_ADDR_HI				0x00000805
995 #define REG_A6XX_CP_RB_RPTR					0x00000806
997 #define REG_A6XX_CP_RB_WPTR					0x00000807
999 #define REG_A6XX_CP_SQE_CNTL					0x00000808
1001 #define REG_A6XX_CP_CP2GMU_STATUS				0x00000812
1002 #define A6XX_CP_CP2GMU_STATUS_IFPC				0x00000001
1004 #define REG_A6XX_CP_HW_FAULT					0x00000821
1006 #define REG_A6XX_CP_INTERRUPT_STATUS				0x00000823
1008 #define REG_A6XX_CP_PROTECT_STATUS				0x00000824
1010 #define REG_A6XX_CP_SQE_INSTR_BASE_LO				0x00000830
1012 #define REG_A6XX_CP_SQE_INSTR_BASE_HI				0x00000831
1014 #define REG_A6XX_CP_MISC_CNTL					0x00000840
1016 #define REG_A6XX_CP_APRIV_CNTL					0x00000844
1018 #define REG_A6XX_CP_ROQ_THRESHOLDS_1				0x000008c1
1019 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK			0x000000ff
1020 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT			0
1025 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK			0x0000ff00
1031 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK		0x00ff0000
1037 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK		0xff000000
1044 #define REG_A6XX_CP_ROQ_THRESHOLDS_2				0x000008c2
1045 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK		0x000001ff
1046 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT		0
1051 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK			0xffff0000
1058 #define REG_A6XX_CP_MEM_POOL_SIZE				0x000008c3
1060 #define REG_A6XX_CP_CHICKEN_DBG					0x00000841
1062 #define REG_A6XX_CP_ADDR_MODE_CNTL				0x00000842
1064 #define REG_A6XX_CP_DBG_ECO_CNTL				0x00000843
1066 #define REG_A6XX_CP_PROTECT_CNTL				0x0000084f
1068 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }  in REG_A6XX_CP_SCRATCH()
1070 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }  in REG_A6XX_CP_SCRATCH_REG()
1072 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }  in REG_A6XX_CP_PROTECT()
1074 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }  in REG_A6XX_CP_PROTECT_REG()
1075 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0003ffff
1076 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0
1081 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK			0x7ffc0000
1087 #define A6XX_CP_PROTECT_REG_READ				0x80000000
1089 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL				0x000008a0
1091 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO			0x000008a1
1093 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI			0x000008a2
1095 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO	0x000008a3
1097 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI	0x000008a4
1099 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO	0x000008a5
1101 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI	0x000008a6
1103 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO	0x000008a7
1105 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI	0x000008a8
1107 #define REG_A6XX_CP_PERFCTR_CP_SEL_0				0x000008d0
1109 #define REG_A6XX_CP_PERFCTR_CP_SEL_1				0x000008d1
1111 #define REG_A6XX_CP_PERFCTR_CP_SEL_2				0x000008d2
1113 #define REG_A6XX_CP_PERFCTR_CP_SEL_3				0x000008d3
1115 #define REG_A6XX_CP_PERFCTR_CP_SEL_4				0x000008d4
1117 #define REG_A6XX_CP_PERFCTR_CP_SEL_5				0x000008d5
1119 #define REG_A6XX_CP_PERFCTR_CP_SEL_6				0x000008d6
1121 #define REG_A6XX_CP_PERFCTR_CP_SEL_7				0x000008d7
1123 #define REG_A6XX_CP_PERFCTR_CP_SEL_8				0x000008d8
1125 #define REG_A6XX_CP_PERFCTR_CP_SEL_9				0x000008d9
1127 #define REG_A6XX_CP_PERFCTR_CP_SEL_10				0x000008da
1129 #define REG_A6XX_CP_PERFCTR_CP_SEL_11				0x000008db
1131 #define REG_A6XX_CP_PERFCTR_CP_SEL_12				0x000008dc
1133 #define REG_A6XX_CP_PERFCTR_CP_SEL_13				0x000008dd
1135 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO			0x00000900
1137 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI			0x00000901
1139 #define REG_A6XX_CP_CRASH_DUMP_CNTL				0x00000902
1141 #define REG_A6XX_CP_CRASH_DUMP_STATUS				0x00000903
1143 #define REG_A6XX_CP_SQE_STAT_ADDR				0x00000908
1145 #define REG_A6XX_CP_SQE_STAT_DATA				0x00000909
1147 #define REG_A6XX_CP_DRAW_STATE_ADDR				0x0000090a
1149 #define REG_A6XX_CP_DRAW_STATE_DATA				0x0000090b
1151 #define REG_A6XX_CP_ROQ_DBG_ADDR				0x0000090c
1153 #define REG_A6XX_CP_ROQ_DBG_DATA				0x0000090d
1155 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR				0x0000090e
1157 #define REG_A6XX_CP_MEM_POOL_DBG_DATA				0x0000090f
1159 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR				0x00000910
1161 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA				0x00000911
1163 #define REG_A6XX_CP_IB1_BASE					0x00000928
1165 #define REG_A6XX_CP_IB1_BASE_HI					0x00000929
1167 #define REG_A6XX_CP_IB1_REM_SIZE				0x0000092a
1169 #define REG_A6XX_CP_IB2_BASE					0x0000092b
1171 #define REG_A6XX_CP_IB2_BASE_HI					0x0000092c
1173 #define REG_A6XX_CP_IB2_REM_SIZE				0x0000092d
1175 #define REG_A6XX_CP_SDS_BASE					0x0000092e
1177 #define REG_A6XX_CP_SDS_BASE_HI					0x0000092f
1179 #define REG_A6XX_CP_SDS_REM_SIZE				0x0000092e
1181 #define REG_A6XX_CP_BIN_SIZE_ADDRESS				0x00000931
1183 #define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI				0x00000932
1185 #define REG_A6XX_CP_BIN_DATA_ADDR				0x00000934
1187 #define REG_A6XX_CP_BIN_DATA_ADDR_HI				0x00000935
1189 #define REG_A6XX_CP_CSQ_IB1_STAT				0x00000949
1190 #define A6XX_CP_CSQ_IB1_STAT_REM__MASK				0xffff0000
1197 #define REG_A6XX_CP_CSQ_IB2_STAT				0x0000094a
1198 #define A6XX_CP_CSQ_IB2_STAT_REM__MASK				0xffff0000
1205 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO			0x00000980
1207 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI			0x00000981
1209 #define REG_A6XX_CP_AHB_CNTL					0x0000098d
1211 #define REG_A6XX_CP_APERTURE_CNTL_HOST				0x00000a00
1213 #define REG_A6XX_CP_APERTURE_CNTL_CD				0x00000a03
1215 #define REG_A6XX_VSC_ADDR_MODE_CNTL				0x00000c01
1217 #define REG_A6XX_RBBM_INT_0_STATUS				0x00000201
1219 #define REG_A6XX_RBBM_STATUS					0x00000210
1220 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB			0x00800000
1221 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP			0x00400000
1222 #define A6XX_RBBM_STATUS_HLSQ_BUSY				0x00200000
1223 #define A6XX_RBBM_STATUS_VSC_BUSY				0x00100000
1224 #define A6XX_RBBM_STATUS_TPL1_BUSY				0x00080000
1225 #define A6XX_RBBM_STATUS_SP_BUSY				0x00040000
1226 #define A6XX_RBBM_STATUS_UCHE_BUSY				0x00020000
1227 #define A6XX_RBBM_STATUS_VPC_BUSY				0x00010000
1228 #define A6XX_RBBM_STATUS_VFD_BUSY				0x00008000
1229 #define A6XX_RBBM_STATUS_TESS_BUSY				0x00004000
1230 #define A6XX_RBBM_STATUS_PC_VSD_BUSY				0x00002000
1231 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY				0x00001000
1232 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY				0x00000800
1233 #define A6XX_RBBM_STATUS_LRZ_BUSY				0x00000400
1234 #define A6XX_RBBM_STATUS_A2D_BUSY				0x00000200
1235 #define A6XX_RBBM_STATUS_CCU_BUSY				0x00000100
1236 #define A6XX_RBBM_STATUS_RB_BUSY				0x00000080
1237 #define A6XX_RBBM_STATUS_RAS_BUSY				0x00000040
1238 #define A6XX_RBBM_STATUS_TSE_BUSY				0x00000020
1239 #define A6XX_RBBM_STATUS_VBIF_BUSY				0x00000010
1240 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY				0x00000008
1241 #define A6XX_RBBM_STATUS_CP_BUSY				0x00000004
1242 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER			0x00000002
1243 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER			0x00000001
1245 #define REG_A6XX_RBBM_STATUS3					0x00000213
1246 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000
1248 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS			0x00000215
1250 #define REG_A6XX_RBBM_PERFCTR_CP_0_LO				0x00000400
1252 #define REG_A6XX_RBBM_PERFCTR_CP_0_HI				0x00000401
1254 #define REG_A6XX_RBBM_PERFCTR_CP_1_LO				0x00000402
1256 #define REG_A6XX_RBBM_PERFCTR_CP_1_HI				0x00000403
1258 #define REG_A6XX_RBBM_PERFCTR_CP_2_LO				0x00000404
1260 #define REG_A6XX_RBBM_PERFCTR_CP_2_HI				0x00000405
1262 #define REG_A6XX_RBBM_PERFCTR_CP_3_LO				0x00000406
1264 #define REG_A6XX_RBBM_PERFCTR_CP_3_HI				0x00000407
1266 #define REG_A6XX_RBBM_PERFCTR_CP_4_LO				0x00000408
1268 #define REG_A6XX_RBBM_PERFCTR_CP_4_HI				0x00000409
1270 #define REG_A6XX_RBBM_PERFCTR_CP_5_LO				0x0000040a
1272 #define REG_A6XX_RBBM_PERFCTR_CP_5_HI				0x0000040b
1274 #define REG_A6XX_RBBM_PERFCTR_CP_6_LO				0x0000040c
1276 #define REG_A6XX_RBBM_PERFCTR_CP_6_HI				0x0000040d
1278 #define REG_A6XX_RBBM_PERFCTR_CP_7_LO				0x0000040e
1280 #define REG_A6XX_RBBM_PERFCTR_CP_7_HI				0x0000040f
1282 #define REG_A6XX_RBBM_PERFCTR_CP_8_LO				0x00000410
1284 #define REG_A6XX_RBBM_PERFCTR_CP_8_HI				0x00000411
1286 #define REG_A6XX_RBBM_PERFCTR_CP_9_LO				0x00000412
1288 #define REG_A6XX_RBBM_PERFCTR_CP_9_HI				0x00000413
1290 #define REG_A6XX_RBBM_PERFCTR_CP_10_LO				0x00000414
1292 #define REG_A6XX_RBBM_PERFCTR_CP_10_HI				0x00000415
1294 #define REG_A6XX_RBBM_PERFCTR_CP_11_LO				0x00000416
1296 #define REG_A6XX_RBBM_PERFCTR_CP_11_HI				0x00000417
1298 #define REG_A6XX_RBBM_PERFCTR_CP_12_LO				0x00000418
1300 #define REG_A6XX_RBBM_PERFCTR_CP_12_HI				0x00000419
1302 #define REG_A6XX_RBBM_PERFCTR_CP_13_LO				0x0000041a
1304 #define REG_A6XX_RBBM_PERFCTR_CP_13_HI				0x0000041b
1306 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO				0x0000041c
1308 #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI				0x0000041d
1310 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO				0x0000041e
1312 #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI				0x0000041f
1314 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO				0x00000420
1316 #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI				0x00000421
1318 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO				0x00000422
1320 #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI				0x00000423
1322 #define REG_A6XX_RBBM_PERFCTR_PC_0_LO				0x00000424
1324 #define REG_A6XX_RBBM_PERFCTR_PC_0_HI				0x00000425
1326 #define REG_A6XX_RBBM_PERFCTR_PC_1_LO				0x00000426
1328 #define REG_A6XX_RBBM_PERFCTR_PC_1_HI				0x00000427
1330 #define REG_A6XX_RBBM_PERFCTR_PC_2_LO				0x00000428
1332 #define REG_A6XX_RBBM_PERFCTR_PC_2_HI				0x00000429
1334 #define REG_A6XX_RBBM_PERFCTR_PC_3_LO				0x0000042a
1336 #define REG_A6XX_RBBM_PERFCTR_PC_3_HI				0x0000042b
1338 #define REG_A6XX_RBBM_PERFCTR_PC_4_LO				0x0000042c
1340 #define REG_A6XX_RBBM_PERFCTR_PC_4_HI				0x0000042d
1342 #define REG_A6XX_RBBM_PERFCTR_PC_5_LO				0x0000042e
1344 #define REG_A6XX_RBBM_PERFCTR_PC_5_HI				0x0000042f
1346 #define REG_A6XX_RBBM_PERFCTR_PC_6_LO				0x00000430
1348 #define REG_A6XX_RBBM_PERFCTR_PC_6_HI				0x00000431
1350 #define REG_A6XX_RBBM_PERFCTR_PC_7_LO				0x00000432
1352 #define REG_A6XX_RBBM_PERFCTR_PC_7_HI				0x00000433
1354 #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO				0x00000434
1356 #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI				0x00000435
1358 #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO				0x00000436
1360 #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI				0x00000437
1362 #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO				0x00000438
1364 #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI				0x00000439
1366 #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO				0x0000043a
1368 #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI				0x0000043b
1370 #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO				0x0000043c
1372 #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI				0x0000043d
1374 #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO				0x0000043e
1376 #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI				0x0000043f
1378 #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO				0x00000440
1380 #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI				0x00000441
1382 #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO				0x00000442
1384 #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI				0x00000443
1386 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO				0x00000444
1388 #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI				0x00000445
1390 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO				0x00000446
1392 #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI				0x00000447
1394 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO				0x00000448
1396 #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI				0x00000449
1398 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO				0x0000044a
1400 #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI				0x0000044b
1402 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO				0x0000044c
1404 #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI				0x0000044d
1406 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO				0x0000044e
1408 #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI				0x0000044f
1410 #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO				0x00000450
1412 #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI				0x00000451
1414 #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO				0x00000452
1416 #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI				0x00000453
1418 #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO				0x00000454
1420 #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI				0x00000455
1422 #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO				0x00000456
1424 #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI				0x00000457
1426 #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO				0x00000458
1428 #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI				0x00000459
1430 #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO				0x0000045a
1432 #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI				0x0000045b
1434 #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO				0x0000045c
1436 #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI				0x0000045d
1438 #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO				0x0000045e
1440 #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI				0x0000045f
1442 #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO				0x00000460
1444 #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI				0x00000461
1446 #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO				0x00000462
1448 #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI				0x00000463
1450 #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO				0x00000464
1452 #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI				0x00000465
1454 #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO				0x00000466
1456 #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI				0x00000467
1458 #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO				0x00000468
1460 #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI				0x00000469
1462 #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO				0x0000046a
1464 #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI				0x0000046b
1466 #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO				0x0000046c
1468 #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI				0x0000046d
1470 #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO				0x0000046e
1472 #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI				0x0000046f
1474 #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO				0x00000470
1476 #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI				0x00000471
1478 #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO				0x00000472
1480 #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI				0x00000473
1482 #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO				0x00000474
1484 #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI				0x00000475
1486 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO				0x00000476
1488 #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI				0x00000477
1490 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO				0x00000478
1492 #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI				0x00000479
1494 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO				0x0000047a
1496 #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI				0x0000047b
1498 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO				0x0000047c
1500 #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI				0x0000047d
1502 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO				0x0000047e
1504 #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI				0x0000047f
1506 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO				0x00000480
1508 #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI				0x00000481
1510 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO				0x00000482
1512 #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI				0x00000483
1514 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO				0x00000484
1516 #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI				0x00000485
1518 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO				0x00000486
1520 #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI				0x00000487
1522 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO				0x00000488
1524 #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI				0x00000489
1526 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO			0x0000048a
1528 #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI			0x0000048b
1530 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO			0x0000048c
1532 #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI			0x0000048d
1534 #define REG_A6XX_RBBM_PERFCTR_TP_0_LO				0x0000048e
1536 #define REG_A6XX_RBBM_PERFCTR_TP_0_HI				0x0000048f
1538 #define REG_A6XX_RBBM_PERFCTR_TP_1_LO				0x00000490
1540 #define REG_A6XX_RBBM_PERFCTR_TP_1_HI				0x00000491
1542 #define REG_A6XX_RBBM_PERFCTR_TP_2_LO				0x00000492
1544 #define REG_A6XX_RBBM_PERFCTR_TP_2_HI				0x00000493
1546 #define REG_A6XX_RBBM_PERFCTR_TP_3_LO				0x00000494
1548 #define REG_A6XX_RBBM_PERFCTR_TP_3_HI				0x00000495
1550 #define REG_A6XX_RBBM_PERFCTR_TP_4_LO				0x00000496
1552 #define REG_A6XX_RBBM_PERFCTR_TP_4_HI				0x00000497
1554 #define REG_A6XX_RBBM_PERFCTR_TP_5_LO				0x00000498
1556 #define REG_A6XX_RBBM_PERFCTR_TP_5_HI				0x00000499
1558 #define REG_A6XX_RBBM_PERFCTR_TP_6_LO				0x0000049a
1560 #define REG_A6XX_RBBM_PERFCTR_TP_6_HI				0x0000049b
1562 #define REG_A6XX_RBBM_PERFCTR_TP_7_LO				0x0000049c
1564 #define REG_A6XX_RBBM_PERFCTR_TP_7_HI				0x0000049d
1566 #define REG_A6XX_RBBM_PERFCTR_TP_8_LO				0x0000049e
1568 #define REG_A6XX_RBBM_PERFCTR_TP_8_HI				0x0000049f
1570 #define REG_A6XX_RBBM_PERFCTR_TP_9_LO				0x000004a0
1572 #define REG_A6XX_RBBM_PERFCTR_TP_9_HI				0x000004a1
1574 #define REG_A6XX_RBBM_PERFCTR_TP_10_LO				0x000004a2
1576 #define REG_A6XX_RBBM_PERFCTR_TP_10_HI				0x000004a3
1578 #define REG_A6XX_RBBM_PERFCTR_TP_11_LO				0x000004a4
1580 #define REG_A6XX_RBBM_PERFCTR_TP_11_HI				0x000004a5
1582 #define REG_A6XX_RBBM_PERFCTR_SP_0_LO				0x000004a6
1584 #define REG_A6XX_RBBM_PERFCTR_SP_0_HI				0x000004a7
1586 #define REG_A6XX_RBBM_PERFCTR_SP_1_LO				0x000004a8
1588 #define REG_A6XX_RBBM_PERFCTR_SP_1_HI				0x000004a9
1590 #define REG_A6XX_RBBM_PERFCTR_SP_2_LO				0x000004aa
1592 #define REG_A6XX_RBBM_PERFCTR_SP_2_HI				0x000004ab
1594 #define REG_A6XX_RBBM_PERFCTR_SP_3_LO				0x000004ac
1596 #define REG_A6XX_RBBM_PERFCTR_SP_3_HI				0x000004ad
1598 #define REG_A6XX_RBBM_PERFCTR_SP_4_LO				0x000004ae
1600 #define REG_A6XX_RBBM_PERFCTR_SP_4_HI				0x000004af
1602 #define REG_A6XX_RBBM_PERFCTR_SP_5_LO				0x000004b0
1604 #define REG_A6XX_RBBM_PERFCTR_SP_5_HI				0x000004b1
1606 #define REG_A6XX_RBBM_PERFCTR_SP_6_LO				0x000004b2
1608 #define REG_A6XX_RBBM_PERFCTR_SP_6_HI				0x000004b3
1610 #define REG_A6XX_RBBM_PERFCTR_SP_7_LO				0x000004b4
1612 #define REG_A6XX_RBBM_PERFCTR_SP_7_HI				0x000004b5
1614 #define REG_A6XX_RBBM_PERFCTR_SP_8_LO				0x000004b6
1616 #define REG_A6XX_RBBM_PERFCTR_SP_8_HI				0x000004b7
1618 #define REG_A6XX_RBBM_PERFCTR_SP_9_LO				0x000004b8
1620 #define REG_A6XX_RBBM_PERFCTR_SP_9_HI				0x000004b9
1622 #define REG_A6XX_RBBM_PERFCTR_SP_10_LO				0x000004ba
1624 #define REG_A6XX_RBBM_PERFCTR_SP_10_HI				0x000004bb
1626 #define REG_A6XX_RBBM_PERFCTR_SP_11_LO				0x000004bc
1628 #define REG_A6XX_RBBM_PERFCTR_SP_11_HI				0x000004bd
1630 #define REG_A6XX_RBBM_PERFCTR_SP_12_LO				0x000004be
1632 #define REG_A6XX_RBBM_PERFCTR_SP_12_HI				0x000004bf
1634 #define REG_A6XX_RBBM_PERFCTR_SP_13_LO				0x000004c0
1636 #define REG_A6XX_RBBM_PERFCTR_SP_13_HI				0x000004c1
1638 #define REG_A6XX_RBBM_PERFCTR_SP_14_LO				0x000004c2
1640 #define REG_A6XX_RBBM_PERFCTR_SP_14_HI				0x000004c3
1642 #define REG_A6XX_RBBM_PERFCTR_SP_15_LO				0x000004c4
1644 #define REG_A6XX_RBBM_PERFCTR_SP_15_HI				0x000004c5
1646 #define REG_A6XX_RBBM_PERFCTR_SP_16_LO				0x000004c6
1648 #define REG_A6XX_RBBM_PERFCTR_SP_16_HI				0x000004c7
1650 #define REG_A6XX_RBBM_PERFCTR_SP_17_LO				0x000004c8
1652 #define REG_A6XX_RBBM_PERFCTR_SP_17_HI				0x000004c9
1654 #define REG_A6XX_RBBM_PERFCTR_SP_18_LO				0x000004ca
1656 #define REG_A6XX_RBBM_PERFCTR_SP_18_HI				0x000004cb
1658 #define REG_A6XX_RBBM_PERFCTR_SP_19_LO				0x000004cc
1660 #define REG_A6XX_RBBM_PERFCTR_SP_19_HI				0x000004cd
1662 #define REG_A6XX_RBBM_PERFCTR_SP_20_LO				0x000004ce
1664 #define REG_A6XX_RBBM_PERFCTR_SP_20_HI				0x000004cf
1666 #define REG_A6XX_RBBM_PERFCTR_SP_21_LO				0x000004d0
1668 #define REG_A6XX_RBBM_PERFCTR_SP_21_HI				0x000004d1
1670 #define REG_A6XX_RBBM_PERFCTR_SP_22_LO				0x000004d2
1672 #define REG_A6XX_RBBM_PERFCTR_SP_22_HI				0x000004d3
1674 #define REG_A6XX_RBBM_PERFCTR_SP_23_LO				0x000004d4
1676 #define REG_A6XX_RBBM_PERFCTR_SP_23_HI				0x000004d5
1678 #define REG_A6XX_RBBM_PERFCTR_RB_0_LO				0x000004d6
1680 #define REG_A6XX_RBBM_PERFCTR_RB_0_HI				0x000004d7
1682 #define REG_A6XX_RBBM_PERFCTR_RB_1_LO				0x000004d8
1684 #define REG_A6XX_RBBM_PERFCTR_RB_1_HI				0x000004d9
1686 #define REG_A6XX_RBBM_PERFCTR_RB_2_LO				0x000004da
1688 #define REG_A6XX_RBBM_PERFCTR_RB_2_HI				0x000004db
1690 #define REG_A6XX_RBBM_PERFCTR_RB_3_LO				0x000004dc
1692 #define REG_A6XX_RBBM_PERFCTR_RB_3_HI				0x000004dd
1694 #define REG_A6XX_RBBM_PERFCTR_RB_4_LO				0x000004de
1696 #define REG_A6XX_RBBM_PERFCTR_RB_4_HI				0x000004df
1698 #define REG_A6XX_RBBM_PERFCTR_RB_5_LO				0x000004e0
1700 #define REG_A6XX_RBBM_PERFCTR_RB_5_HI				0x000004e1
1702 #define REG_A6XX_RBBM_PERFCTR_RB_6_LO				0x000004e2
1704 #define REG_A6XX_RBBM_PERFCTR_RB_6_HI				0x000004e3
1706 #define REG_A6XX_RBBM_PERFCTR_RB_7_LO				0x000004e4
1708 #define REG_A6XX_RBBM_PERFCTR_RB_7_HI				0x000004e5
1710 #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO				0x000004e6
1712 #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI				0x000004e7
1714 #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO				0x000004e8
1716 #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI				0x000004e9
1718 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO				0x000004ea
1720 #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI				0x000004eb
1722 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO				0x000004ec
1724 #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI				0x000004ed
1726 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO				0x000004ee
1728 #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI				0x000004ef
1730 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO				0x000004f0
1732 #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI				0x000004f1
1734 #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO				0x000004f2
1736 #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI				0x000004f3
1738 #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO				0x000004f4
1740 #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI				0x000004f5
1742 #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO				0x000004f6
1744 #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI				0x000004f7
1746 #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO				0x000004f8
1748 #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI				0x000004f9
1750 #define REG_A6XX_RBBM_PERFCTR_CNTL				0x00000500
1752 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0				0x00000501
1754 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1				0x00000502
1756 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2				0x00000503
1758 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3				0x00000504
1760 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000505
1762 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000506
1764 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0			0x00000507
1766 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1			0x00000508
1768 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2			0x00000509
1770 #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3			0x0000050a
1772 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED			0x0000050b
1774 #define REG_A6XX_RBBM_ISDB_CNT					0x00000533
1776 #define REG_A6XX_RBBM_PRIMCTR_0_LO				0x00000540
1778 #define REG_A6XX_RBBM_PRIMCTR_0_HI				0x00000541
1780 #define REG_A6XX_RBBM_PRIMCTR_1_LO				0x00000542
1782 #define REG_A6XX_RBBM_PRIMCTR_1_HI				0x00000543
1784 #define REG_A6XX_RBBM_PRIMCTR_2_LO				0x00000544
1786 #define REG_A6XX_RBBM_PRIMCTR_2_HI				0x00000545
1788 #define REG_A6XX_RBBM_PRIMCTR_3_LO				0x00000546
1790 #define REG_A6XX_RBBM_PRIMCTR_3_HI				0x00000547
1792 #define REG_A6XX_RBBM_PRIMCTR_4_LO				0x00000548
1794 #define REG_A6XX_RBBM_PRIMCTR_4_HI				0x00000549
1796 #define REG_A6XX_RBBM_PRIMCTR_5_LO				0x0000054a
1798 #define REG_A6XX_RBBM_PRIMCTR_5_HI				0x0000054b
1800 #define REG_A6XX_RBBM_PRIMCTR_6_LO				0x0000054c
1802 #define REG_A6XX_RBBM_PRIMCTR_6_HI				0x0000054d
1804 #define REG_A6XX_RBBM_PRIMCTR_7_LO				0x0000054e
1806 #define REG_A6XX_RBBM_PRIMCTR_7_HI				0x0000054f
1808 #define REG_A6XX_RBBM_PRIMCTR_8_LO				0x00000550
1810 #define REG_A6XX_RBBM_PRIMCTR_8_HI				0x00000551
1812 #define REG_A6XX_RBBM_PRIMCTR_9_LO				0x00000552
1814 #define REG_A6XX_RBBM_PRIMCTR_9_HI				0x00000553
1816 #define REG_A6XX_RBBM_PRIMCTR_10_LO				0x00000554
1818 #define REG_A6XX_RBBM_PRIMCTR_10_HI				0x00000555
1820 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL				0x0000f400
1822 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO		0x0000f800
1824 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI		0x0000f801
1826 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE			0x0000f802
1828 #define REG_A6XX_RBBM_SECVID_TSB_CNTL				0x0000f803
1830 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL			0x0000f810
1832 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL			0x00000010
1834 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL			0x00000011
1836 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD			0x0000001c
1837 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE		0x00000001
1839 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL			0x0000001f
1841 #define REG_A6XX_RBBM_INT_CLEAR_CMD				0x00000037
1843 #define REG_A6XX_RBBM_INT_0_MASK				0x00000038
1845 #define REG_A6XX_RBBM_SP_HYST_CNT				0x00000042
1847 #define REG_A6XX_RBBM_SW_RESET_CMD				0x00000043
1849 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT				0x00000044
1851 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD			0x00000045
1853 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2			0x00000046
1855 #define REG_A6XX_RBBM_CLOCK_CNTL				0x000000ae
1857 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0				0x000000b0
1859 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1				0x000000b1
1861 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2				0x000000b2
1863 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3				0x000000b3
1865 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0				0x000000b4
1867 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1				0x000000b5
1869 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2				0x000000b6
1871 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3				0x000000b7
1873 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0				0x000000b8
1875 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1				0x000000b9
1877 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2				0x000000ba
1879 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3				0x000000bb
1881 #define REG_A6XX_RBBM_CLOCK_HYST_SP0				0x000000bc
1883 #define REG_A6XX_RBBM_CLOCK_HYST_SP1				0x000000bd
1885 #define REG_A6XX_RBBM_CLOCK_HYST_SP2				0x000000be
1887 #define REG_A6XX_RBBM_CLOCK_HYST_SP3				0x000000bf
1889 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0				0x000000c0
1891 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1				0x000000c1
1893 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2				0x000000c2
1895 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3				0x000000c3
1897 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0				0x000000c4
1899 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1				0x000000c5
1901 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2				0x000000c6
1903 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3				0x000000c7
1905 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0				0x000000c8
1907 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1				0x000000c9
1909 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2				0x000000ca
1911 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3				0x000000cb
1913 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0				0x000000cc
1915 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1				0x000000cd
1917 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2				0x000000ce
1919 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3				0x000000cf
1921 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0				0x000000d0
1923 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1				0x000000d1
1925 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2				0x000000d2
1927 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3				0x000000d3
1929 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0				0x000000d4
1931 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1				0x000000d5
1933 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2				0x000000d6
1935 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3				0x000000d7
1937 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0				0x000000d8
1939 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1				0x000000d9
1941 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2				0x000000da
1943 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3				0x000000db
1945 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0				0x000000dc
1947 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1				0x000000dd
1949 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2				0x000000de
1951 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3				0x000000df
1953 #define REG_A6XX_RBBM_CLOCK_HYST_TP0				0x000000e0
1955 #define REG_A6XX_RBBM_CLOCK_HYST_TP1				0x000000e1
1957 #define REG_A6XX_RBBM_CLOCK_HYST_TP2				0x000000e2
1959 #define REG_A6XX_RBBM_CLOCK_HYST_TP3				0x000000e3
1961 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0				0x000000e4
1963 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1				0x000000e5
1965 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2				0x000000e6
1967 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3				0x000000e7
1969 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0				0x000000e8
1971 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1				0x000000e9
1973 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2				0x000000ea
1975 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3				0x000000eb
1977 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0				0x000000ec
1979 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1				0x000000ed
1981 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2				0x000000ee
1983 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3				0x000000ef
1985 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0				0x000000f0
1987 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1				0x000000f1
1989 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2				0x000000f2
1991 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3				0x000000f3
1993 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0				0x000000f4
1995 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1				0x000000f5
1997 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2				0x000000f6
1999 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3				0x000000f7
2001 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0				0x000000f8
2003 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1				0x000000f9
2005 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2				0x000000fa
2007 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3				0x000000fb
2009 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0			0x00000100
2011 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1			0x00000101
2013 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2			0x00000102
2015 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3			0x00000103
2017 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC				0x00000104
2019 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC				0x00000105
2021 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC				0x00000106
2023 #define REG_A6XX_RBBM_CLOCK_HYST_RAC				0x00000107
2025 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM			0x00000108
2027 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM			0x00000109
2029 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM			0x0000010a
2031 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE				0x0000010b
2033 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE				0x0000010c
2035 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE				0x0000010d
2037 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE				0x0000010e
2039 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE				0x0000010f
2041 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE				0x00000110
2043 #define REG_A6XX_RBBM_CLOCK_MODE_VFD				0x00000111
2045 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD				0x00000112
2047 #define REG_A6XX_RBBM_CLOCK_HYST_VFD				0x00000113
2049 #define REG_A6XX_RBBM_CLOCK_MODE_GPC				0x00000114
2051 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC				0x00000115
2053 #define REG_A6XX_RBBM_CLOCK_HYST_GPC				0x00000116
2055 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2			0x00000117
2057 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX				0x00000118
2059 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX			0x00000119
2061 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX				0x0000011a
2063 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ				0x0000011b
2065 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ				0x0000011c
2067 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ				0x0000011d
2069 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE			0x00000120
2071 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE			0x00000121
2073 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE			0x00000122
2075 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A				0x00000600
2077 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B				0x00000601
2079 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C				0x00000602
2081 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D				0x00000603
2082 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK		0x000000ff
2083 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT		0
2088 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK		0x0000ff00
2095 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT				0x00000604
2096 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
2097 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
2102 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK			0x00007000
2108 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK			0xf0000000
2115 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM				0x00000605
2116 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK			0x0f000000
2123 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0				0x00000608
2125 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1				0x00000609
2127 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2				0x0000060a
2129 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3				0x0000060b
2131 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0			0x0000060c
2133 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1			0x0000060d
2135 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2			0x0000060e
2137 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3			0x0000060f
2139 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000610
2140 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
2141 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
2146 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
2152 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
2158 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
2164 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
2170 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
2176 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
2182 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
2189 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000611
2190 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
2191 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
2196 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
2202 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
2208 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
2214 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
2220 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
2226 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
2232 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
2239 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000062f
2241 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000630
2243 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0				0x00000cd8
2245 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1				0x00000cd9
2247 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL				0x0000be05
2249 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0			0x0000be10
2251 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1			0x0000be11
2253 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2			0x0000be12
2255 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3			0x0000be13
2257 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4			0x0000be14
2259 #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5			0x0000be15
2261 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE			0x0000c800
2263 #define REG_A6XX_HLSQ_DBG_READ_SEL				0x0000d000
2265 #define REG_A6XX_VFD_ADDR_MODE_CNTL				0x0000a601
2267 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0				0x0000a610
2269 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1				0x0000a611
2271 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2				0x0000a612
2273 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3				0x0000a613
2275 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4				0x0000a614
2277 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5				0x0000a615
2279 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6				0x0000a616
2281 #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7				0x0000a617
2283 #define REG_A6XX_UCHE_ADDR_MODE_CNTL				0x00000e00
2285 #define REG_A6XX_UCHE_MODE_CNTL					0x00000e01
2287 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO			0x00000e05
2289 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI			0x00000e06
2291 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO			0x00000e07
2293 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI			0x00000e08
2295 #define REG_A6XX_UCHE_TRAP_BASE_LO				0x00000e09
2297 #define REG_A6XX_UCHE_TRAP_BASE_HI				0x00000e0a
2299 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO				0x00000e0b
2301 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI				0x00000e0c
2303 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO				0x00000e0d
2305 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI				0x00000e0e
2307 #define REG_A6XX_UCHE_CACHE_WAYS				0x00000e17
2309 #define REG_A6XX_UCHE_FILTER_CNTL				0x00000e18
2311 #define REG_A6XX_UCHE_CLIENT_PF					0x00000e19
2312 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK			0x000000ff
2313 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT			0
2319 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0			0x00000e1c
2321 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1			0x00000e1d
2323 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2			0x00000e1e
2325 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3			0x00000e1f
2327 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4			0x00000e20
2329 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5			0x00000e21
2331 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6			0x00000e22
2333 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7			0x00000e23
2335 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8			0x00000e24
2337 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9			0x00000e25
2339 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10			0x00000e26
2341 #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11			0x00000e27
2343 #define REG_A6XX_SP_ADDR_MODE_CNTL				0x0000ae01
2345 #define REG_A6XX_SP_NC_MODE_CNTL				0x0000ae02
2347 #define REG_A6XX_SP_PERFCTR_SP_SEL_0				0x0000ae10
2349 #define REG_A6XX_SP_PERFCTR_SP_SEL_1				0x0000ae11
2351 #define REG_A6XX_SP_PERFCTR_SP_SEL_2				0x0000ae12
2353 #define REG_A6XX_SP_PERFCTR_SP_SEL_3				0x0000ae13
2355 #define REG_A6XX_SP_PERFCTR_SP_SEL_4				0x0000ae14
2357 #define REG_A6XX_SP_PERFCTR_SP_SEL_5				0x0000ae15
2359 #define REG_A6XX_SP_PERFCTR_SP_SEL_6				0x0000ae16
2361 #define REG_A6XX_SP_PERFCTR_SP_SEL_7				0x0000ae17
2363 #define REG_A6XX_SP_PERFCTR_SP_SEL_8				0x0000ae18
2365 #define REG_A6XX_SP_PERFCTR_SP_SEL_9				0x0000ae19
2367 #define REG_A6XX_SP_PERFCTR_SP_SEL_10				0x0000ae1a
2369 #define REG_A6XX_SP_PERFCTR_SP_SEL_11				0x0000ae1b
2371 #define REG_A6XX_SP_PERFCTR_SP_SEL_12				0x0000ae1c
2373 #define REG_A6XX_SP_PERFCTR_SP_SEL_13				0x0000ae1d
2375 #define REG_A6XX_SP_PERFCTR_SP_SEL_14				0x0000ae1e
2377 #define REG_A6XX_SP_PERFCTR_SP_SEL_15				0x0000ae1f
2379 #define REG_A6XX_SP_PERFCTR_SP_SEL_16				0x0000ae20
2381 #define REG_A6XX_SP_PERFCTR_SP_SEL_17				0x0000ae21
2383 #define REG_A6XX_SP_PERFCTR_SP_SEL_18				0x0000ae22
2385 #define REG_A6XX_SP_PERFCTR_SP_SEL_19				0x0000ae23
2387 #define REG_A6XX_SP_PERFCTR_SP_SEL_20				0x0000ae24
2389 #define REG_A6XX_SP_PERFCTR_SP_SEL_21				0x0000ae25
2391 #define REG_A6XX_SP_PERFCTR_SP_SEL_22				0x0000ae26
2393 #define REG_A6XX_SP_PERFCTR_SP_SEL_23				0x0000ae27
2395 #define REG_A6XX_TPL1_ADDR_MODE_CNTL				0x0000b601
2397 #define REG_A6XX_TPL1_NC_MODE_CNTL				0x0000b604
2399 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0			0x0000b608
2401 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1			0x0000b609
2403 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2			0x0000b60a
2405 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3			0x0000b60b
2407 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4			0x0000b60c
2409 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0				0x0000b610
2411 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1				0x0000b611
2413 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2				0x0000b612
2415 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3				0x0000b613
2417 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4				0x0000b614
2419 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5				0x0000b615
2421 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6				0x0000b616
2423 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7				0x0000b617
2425 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8				0x0000b618
2427 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9				0x0000b619
2429 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10				0x0000b61a
2431 #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11				0x0000b61b
2433 #define REG_A6XX_VBIF_VERSION					0x00003000
2435 #define REG_A6XX_VBIF_CLKON					0x00003001
2436 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS			0x00000002
2438 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
2440 #define REG_A6XX_VBIF_XIN_HALT_CTRL0				0x00003080
2442 #define REG_A6XX_VBIF_XIN_HALT_CTRL1				0x00003081
2444 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL				0x00003084
2446 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0				0x00003085
2448 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1				0x00003086
2449 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK		0x0000000f
2450 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT		0
2456 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0				0x00003087
2458 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1				0x00003088
2459 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK		0x000001ff
2460 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT		0
2466 #define REG_A6XX_VBIF_TEST_BUS_OUT				0x0000308c
2468 #define REG_A6XX_VBIF_PERF_CNT_SEL0				0x000030d0
2470 #define REG_A6XX_VBIF_PERF_CNT_SEL1				0x000030d1
2472 #define REG_A6XX_VBIF_PERF_CNT_SEL2				0x000030d2
2474 #define REG_A6XX_VBIF_PERF_CNT_SEL3				0x000030d3
2476 #define REG_A6XX_VBIF_PERF_CNT_LOW0				0x000030d8
2478 #define REG_A6XX_VBIF_PERF_CNT_LOW1				0x000030d9
2480 #define REG_A6XX_VBIF_PERF_CNT_LOW2				0x000030da
2482 #define REG_A6XX_VBIF_PERF_CNT_LOW3				0x000030db
2484 #define REG_A6XX_VBIF_PERF_CNT_HIGH0				0x000030e0
2486 #define REG_A6XX_VBIF_PERF_CNT_HIGH1				0x000030e1
2488 #define REG_A6XX_VBIF_PERF_CNT_HIGH2				0x000030e2
2490 #define REG_A6XX_VBIF_PERF_CNT_HIGH3				0x000030e3
2492 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0				0x00003100
2494 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1				0x00003101
2496 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2				0x00003102
2498 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0				0x00003110
2500 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1				0x00003111
2502 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2				0x00003112
2504 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0			0x00003118
2506 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1			0x00003119
2508 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2			0x0000311a
2510 #define REG_A6XX_GBIF_SCACHE_CNTL1				0x00003c02
2512 #define REG_A6XX_GBIF_QSB_SIDE0					0x00003c03
2514 #define REG_A6XX_GBIF_QSB_SIDE1					0x00003c04
2516 #define REG_A6XX_GBIF_QSB_SIDE2					0x00003c05
2518 #define REG_A6XX_GBIF_QSB_SIDE3					0x00003c06
2520 #define REG_A6XX_GBIF_HALT					0x00003c45
2522 #define REG_A6XX_GBIF_HALT_ACK					0x00003c46
2524 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN				0x00003cc0
2526 #define REG_A6XX_GBIF_PERF_CNT_SEL				0x00003cc2
2528 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL				0x00003cc3
2530 #define REG_A6XX_GBIF_PERF_CNT_LOW0				0x00003cc4
2532 #define REG_A6XX_GBIF_PERF_CNT_LOW1				0x00003cc5
2534 #define REG_A6XX_GBIF_PERF_CNT_LOW2				0x00003cc6
2536 #define REG_A6XX_GBIF_PERF_CNT_LOW3				0x00003cc7
2538 #define REG_A6XX_GBIF_PERF_CNT_HIGH0				0x00003cc8
2540 #define REG_A6XX_GBIF_PERF_CNT_HIGH1				0x00003cc9
2542 #define REG_A6XX_GBIF_PERF_CNT_HIGH2				0x00003cca
2544 #define REG_A6XX_GBIF_PERF_CNT_HIGH3				0x00003ccb
2546 #define REG_A6XX_GBIF_PWR_CNT_LOW0				0x00003ccc
2548 #define REG_A6XX_GBIF_PWR_CNT_LOW1				0x00003ccd
2550 #define REG_A6XX_GBIF_PWR_CNT_LOW2				0x00003cce
2552 #define REG_A6XX_GBIF_PWR_CNT_HIGH0				0x00003ccf
2554 #define REG_A6XX_GBIF_PWR_CNT_HIGH1				0x00003cd0
2556 #define REG_A6XX_GBIF_PWR_CNT_HIGH2				0x00003cd1
2558 #define REG_A6XX_SP_WINDOW_OFFSET				0x0000b4d1
2559 #define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
2560 #define A6XX_SP_WINDOW_OFFSET_X__MASK				0x00007fff
2561 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT				0
2566 #define A6XX_SP_WINDOW_OFFSET_Y__MASK				0x7fff0000
2573 #define REG_A6XX_SP_TP_WINDOW_OFFSET				0x0000b307
2574 #define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
2575 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK			0x00007fff
2576 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT			0
2581 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK			0x7fff0000
2588 #define REG_A6XX_VSC_BIN_SIZE					0x00000c02
2589 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK				0x000000ff
2590 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
2595 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK				0x0001ff00
2602 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO			0x00000c03
2604 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI			0x00000c04
2606 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS			0x00000c03
2608 #define REG_A6XX_VSC_BIN_COUNT					0x00000c06
2609 #define A6XX_VSC_BIN_COUNT_NX__MASK				0x000007fe
2615 #define A6XX_VSC_BIN_COUNT_NY__MASK				0x001ff800
2622 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }  in REG_A6XX_VSC_PIPE_CONFIG()
2624 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }  in REG_A6XX_VSC_PIPE_CONFIG_REG()
2625 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK			0x000003ff
2626 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT			0
2631 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK			0x000ffc00
2637 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK			0x03f00000
2643 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK			0xfc000000
2650 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO			0x00000c30
2652 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI			0x00000c31
2654 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS				0x00000c30
2656 #define REG_A6XX_VSC_PRIM_STRM_PITCH				0x00000c32
2658 #define REG_A6XX_VSC_PRIM_STRM_LIMIT				0x00000c33
2660 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO			0x00000c34
2662 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI			0x00000c35
2664 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS				0x00000c34
2666 #define REG_A6XX_VSC_DRAW_STRM_PITCH				0x00000c36
2668 #define REG_A6XX_VSC_DRAW_STRM_LIMIT				0x00000c37
2670 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }  in REG_A6XX_VSC_STATE()
2672 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }  in REG_A6XX_VSC_STATE_REG()
2674 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }  in REG_A6XX_VSC_PRIM_STRM_SIZE()
2676 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }  in REG_A6XX_VSC_PRIM_STRM_SIZE_REG()
2678 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }  in REG_A6XX_VSC_DRAW_STRM_SIZE()
2680 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }  in REG_A6XX_VSC_DRAW_STRM_SIZE_REG()
2682 #define REG_A6XX_UCHE_UNKNOWN_0E12				0x00000e12
2684 #define REG_A6XX_GRAS_CL_CNTL					0x00008000
2685 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE				0x00000001
2686 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE			0x00000002
2687 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE			0x00000004
2688 #define A6XX_GRAS_CL_CNTL_UNK5					0x00000020
2689 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040
2690 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE			0x00000080
2691 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE			0x00000100
2692 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE		0x00000200
2694 #define REG_A6XX_GRAS_VS_CL_CNTL				0x00008001
2695 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2696 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0
2701 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2708 #define REG_A6XX_GRAS_DS_CL_CNTL				0x00008002
2709 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2710 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT			0
2715 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2722 #define REG_A6XX_GRAS_GS_CL_CNTL				0x00008003
2723 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2724 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT			0
2729 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2736 #define REG_A6XX_GRAS_MAX_LAYER_INDEX				0x00008004
2738 #define REG_A6XX_GRAS_CNTL					0x00008005
2739 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL				0x00000001
2740 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID			0x00000002
2741 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE				0x00000004
2742 #define A6XX_GRAS_CNTL_SIZE					0x00000008
2743 #define A6XX_GRAS_CNTL_UNK4					0x00000010
2744 #define A6XX_GRAS_CNTL_SIZE_PERSAMP				0x00000020
2745 #define A6XX_GRAS_CNTL_COORD_MASK__MASK				0x000003c0
2752 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ			0x00008006
2753 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000001ff
2754 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT		0
2759 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK		0x0007fc00
2766 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT()
2768 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_XOFFSET()
2769 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK			0xffffffff
2770 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT			0
2776 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_XSCALE()
2777 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK				0xffffffff
2778 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT			0
2784 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_YOFFSET()
2785 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK			0xffffffff
2786 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT			0
2792 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_YSCALE()
2793 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK				0xffffffff
2794 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT			0
2800 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_ZOFFSET()
2801 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK			0xffffffff
2802 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT			0
2808 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_ZSCALE()
2809 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK				0xffffffff
2810 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT			0
2816 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP()
2818 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP_MIN()
2819 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK				0xffffffff
2820 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT				0
2826 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP_MAX()
2827 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK				0xffffffff
2828 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT				0
2834 #define REG_A6XX_GRAS_SU_CNTL					0x00008090
2835 #define A6XX_GRAS_SU_CNTL_CULL_FRONT				0x00000001
2836 #define A6XX_GRAS_SU_CNTL_CULL_BACK				0x00000002
2837 #define A6XX_GRAS_SU_CNTL_FRONT_CW				0x00000004
2838 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK			0x000007f8
2844 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET				0x00000800
2845 #define A6XX_GRAS_SU_CNTL_UNK12__MASK				0x00001000
2851 #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE				0x00002000
2852 #define A6XX_GRAS_SU_CNTL_UNK15__MASK				0x007f8000
2859 #define REG_A6XX_GRAS_SU_POINT_MINMAX				0x00008091
2860 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
2861 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
2866 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
2873 #define REG_A6XX_GRAS_SU_POINT_SIZE				0x00008092
2874 #define A6XX_GRAS_SU_POINT_SIZE__MASK				0x0000ffff
2875 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT				0
2881 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL			0x00008094
2882 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK		0x00000003
2883 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT		0
2889 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE			0x00008095
2890 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
2891 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
2897 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET			0x00008096
2898 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
2899 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
2905 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP		0x00008097
2906 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK		0xffffffff
2907 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT		0
2913 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO			0x00008098
2914 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK	0x00000007
2915 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT	0
2920 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK		0x00000008
2927 #define REG_A6XX_GRAS_UNKNOWN_8099				0x00008099
2929 #define REG_A6XX_GRAS_UNKNOWN_809A				0x0000809a
2931 #define REG_A6XX_GRAS_VS_LAYER_CNTL				0x0000809b
2932 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER			0x00000001
2933 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW			0x00000002
2935 #define REG_A6XX_GRAS_GS_LAYER_CNTL				0x0000809c
2936 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER			0x00000001
2937 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW			0x00000002
2939 #define REG_A6XX_GRAS_DS_LAYER_CNTL				0x0000809d
2940 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER			0x00000001
2941 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW			0x00000002
2943 #define REG_A6XX_GRAS_UNKNOWN_80A0				0x000080a0
2945 #define REG_A6XX_GRAS_BIN_CONTROL				0x000080a1
2946 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK			0x0000003f
2947 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT			0
2952 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK			0x00007f00
2958 #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS			0x00040000
2959 #define A6XX_GRAS_BIN_CONTROL_UNK19__MASK			0x00080000
2965 #define A6XX_GRAS_BIN_CONTROL_UNK20__MASK			0x00100000
2971 #define A6XX_GRAS_BIN_CONTROL_USE_VIZ				0x00200000
2972 #define A6XX_GRAS_BIN_CONTROL_UNK22__MASK			0x0fc00000
2979 #define REG_A6XX_GRAS_RAS_MSAA_CNTL				0x000080a2
2980 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
2981 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
2986 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
2992 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
2999 #define REG_A6XX_GRAS_DEST_MSAA_CNTL				0x000080a3
3000 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
3001 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
3006 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
3008 #define REG_A6XX_GRAS_SAMPLE_CONFIG				0x000080a4
3009 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0				0x00000001
3010 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002
3012 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0				0x000080a5
3013 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
3014 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
3019 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
3025 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
3031 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
3037 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
3043 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
3049 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
3055 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
3062 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1				0x000080a6
3063 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
3064 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
3069 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
3075 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
3081 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
3087 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
3093 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
3099 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
3105 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
3112 #define REG_A6XX_GRAS_UNKNOWN_80AF				0x000080af
3114 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR()
3116 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0…  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL()
3117 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x0000ffff
3118 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
3123 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0xffff0000
3130 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0…  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR()
3131 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x0000ffff
3132 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
3137 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0xffff0000
3144 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0;…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR()
3146 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL()
3147 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK		0x0000ffff
3148 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT		0
3153 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK		0xffff0000
3160 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR()
3161 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK		0x0000ffff
3162 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT		0
3167 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK		0xffff0000
3174 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL			0x000080f0
3175 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00003fff
3176 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
3181 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x3fff0000
3188 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR			0x000080f1
3189 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00003fff
3190 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
3195 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x3fff0000
3202 #define REG_A6XX_GRAS_LRZ_CNTL					0x00008100
3203 #define A6XX_GRAS_LRZ_CNTL_ENABLE				0x00000001
3204 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE				0x00000002
3205 #define A6XX_GRAS_LRZ_CNTL_GREATER				0x00000004
3206 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE				0x00000008
3207 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE			0x00000010
3208 #define A6XX_GRAS_LRZ_CNTL_UNK5__MASK				0x000003e0
3215 #define REG_A6XX_GRAS_UNKNOWN_8101				0x00008101
3217 #define REG_A6XX_GRAS_2D_BLIT_INFO				0x00008102
3218 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK		0x000000ff
3219 #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT		0
3225 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO			0x00008103
3227 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI			0x00008104
3229 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE				0x00008103
3230 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK				0xffffffff
3231 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT			0
3237 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH				0x00008105
3238 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK			0x000000ff
3239 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT			0
3244 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffffc00
3251 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO		0x00008106
3253 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI		0x00008107
3255 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE		0x00008106
3256 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK		0xffffffff
3257 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT		0
3263 #define REG_A6XX_GRAS_SAMPLE_CNTL				0x00008109
3264 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001
3266 #define REG_A6XX_GRAS_UNKNOWN_810A				0x0000810a
3267 #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK			0x000007ff
3268 #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT			0
3273 #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK			0x07ff0000
3279 #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK			0xf0000000
3286 #define REG_A6XX_GRAS_UNKNOWN_8110				0x00008110
3288 #define REG_A6XX_GRAS_2D_BLIT_CNTL				0x00008400
3289 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
3290 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT			0
3295 #define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK			0x00000078
3301 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
3302 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK		0x0000ff00
3308 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR				0x00010000
3309 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK			0x00060000
3315 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8				0x00080000
3316 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK			0x00f00000
3322 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK			0x1f000000
3328 #define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK			0x20000000
3335 #define REG_A6XX_GRAS_2D_SRC_TL_X				0x00008401
3337 #define REG_A6XX_GRAS_2D_SRC_BR_X				0x00008402
3339 #define REG_A6XX_GRAS_2D_SRC_TL_Y				0x00008403
3341 #define REG_A6XX_GRAS_2D_SRC_BR_Y				0x00008404
3343 #define REG_A6XX_GRAS_2D_DST_TL					0x00008405
3344 #define A6XX_GRAS_2D_DST_TL_X__MASK				0x00003fff
3345 #define A6XX_GRAS_2D_DST_TL_X__SHIFT				0
3350 #define A6XX_GRAS_2D_DST_TL_Y__MASK				0x3fff0000
3357 #define REG_A6XX_GRAS_2D_DST_BR					0x00008406
3358 #define A6XX_GRAS_2D_DST_BR_X__MASK				0x00003fff
3359 #define A6XX_GRAS_2D_DST_BR_X__SHIFT				0
3364 #define A6XX_GRAS_2D_DST_BR_Y__MASK				0x3fff0000
3371 #define REG_A6XX_GRAS_2D_UNKNOWN_8407				0x00008407
3373 #define REG_A6XX_GRAS_2D_UNKNOWN_8408				0x00008408
3375 #define REG_A6XX_GRAS_2D_UNKNOWN_8409				0x00008409
3377 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1				0x0000840a
3378 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK			0x00003fff
3379 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT			0
3384 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK			0x3fff0000
3391 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2				0x0000840b
3392 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK			0x00003fff
3393 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT			0
3398 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK			0x3fff0000
3405 #define REG_A6XX_GRAS_UNKNOWN_8600				0x00008600
3407 #define REG_A6XX_GRAS_ADDR_MODE_CNTL				0x00008601
3409 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0				0x00008610
3411 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1				0x00008611
3413 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2				0x00008612
3415 #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3				0x00008613
3417 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0				0x00008614
3419 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1				0x00008615
3421 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2				0x00008616
3423 #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3				0x00008617
3425 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0				0x00008618
3427 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1				0x00008619
3429 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2				0x0000861a
3431 #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3				0x0000861b
3433 #define REG_A6XX_RB_BIN_CONTROL					0x00008800
3434 #define A6XX_RB_BIN_CONTROL_BINW__MASK				0x0000003f
3435 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT				0
3440 #define A6XX_RB_BIN_CONTROL_BINH__MASK				0x00007f00
3446 #define A6XX_RB_BIN_CONTROL_BINNING_PASS			0x00040000
3447 #define A6XX_RB_BIN_CONTROL_UNK19__MASK				0x00080000
3453 #define A6XX_RB_BIN_CONTROL_UNK20__MASK				0x00100000
3459 #define A6XX_RB_BIN_CONTROL_USE_VIZ				0x00200000
3460 #define A6XX_RB_BIN_CONTROL_UNK22__MASK				0x07c00000
3467 #define REG_A6XX_RB_RENDER_CNTL					0x00008801
3468 #define A6XX_RB_RENDER_CNTL_UNK3				0x00000008
3469 #define A6XX_RB_RENDER_CNTL_UNK4				0x00000010
3470 #define A6XX_RB_RENDER_CNTL_UNK5__MASK				0x00000060
3476 #define A6XX_RB_RENDER_CNTL_BINNING				0x00000080
3477 #define A6XX_RB_RENDER_CNTL_UNK8__MASK				0x00001f00
3483 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH				0x00004000
3484 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK			0x00ff0000
3491 #define REG_A6XX_RB_RAS_MSAA_CNTL				0x00008802
3492 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
3493 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
3498 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
3504 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
3511 #define REG_A6XX_RB_DEST_MSAA_CNTL				0x00008803
3512 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
3513 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
3518 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
3520 #define REG_A6XX_RB_SAMPLE_CONFIG				0x00008804
3521 #define A6XX_RB_SAMPLE_CONFIG_UNK0				0x00000001
3522 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002
3524 #define REG_A6XX_RB_SAMPLE_LOCATION_0				0x00008805
3525 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
3526 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
3531 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
3537 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
3543 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
3549 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
3555 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
3561 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
3567 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
3574 #define REG_A6XX_RB_SAMPLE_LOCATION_1				0x00008806
3575 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
3576 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
3581 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
3587 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
3593 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
3599 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
3605 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
3611 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
3617 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
3624 #define REG_A6XX_RB_RENDER_CONTROL0				0x00008809
3625 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL			0x00000001
3626 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID		0x00000002
3627 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE			0x00000004
3628 #define A6XX_RB_RENDER_CONTROL0_SIZE				0x00000008
3629 #define A6XX_RB_RENDER_CONTROL0_UNK4				0x00000010
3630 #define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP			0x00000020
3631 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK		0x000003c0
3637 #define A6XX_RB_RENDER_CONTROL0_UNK10				0x00000400
3639 #define REG_A6XX_RB_RENDER_CONTROL1				0x0000880a
3640 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK			0x00000001
3641 #define A6XX_RB_RENDER_CONTROL1_UNK1				0x00000002
3642 #define A6XX_RB_RENDER_CONTROL1_FACENESS			0x00000004
3643 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID			0x00000008
3644 #define A6XX_RB_RENDER_CONTROL1_UNK4				0x00000010
3645 #define A6XX_RB_RENDER_CONTROL1_UNK5				0x00000020
3646 #define A6XX_RB_RENDER_CONTROL1_SIZE				0x00000040
3647 #define A6XX_RB_RENDER_CONTROL1_UNK7				0x00000080
3648 #define A6XX_RB_RENDER_CONTROL1_UNK8				0x00000100
3650 #define REG_A6XX_RB_FS_OUTPUT_CNTL0				0x0000880b
3651 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
3652 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z			0x00000002
3653 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK		0x00000004
3654 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF		0x00000008
3656 #define REG_A6XX_RB_FS_OUTPUT_CNTL1				0x0000880c
3657 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
3658 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT			0
3664 #define REG_A6XX_RB_RENDER_COMPONENTS				0x0000880d
3665 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
3666 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
3671 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
3677 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
3683 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
3689 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
3695 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
3701 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
3707 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
3714 #define REG_A6XX_RB_DITHER_CNTL					0x0000880e
3715 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK		0x00000003
3716 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT		0
3721 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK		0x0000000c
3727 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK		0x00000030
3733 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK		0x000000c0
3739 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK		0x00000300
3745 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK		0x00000c00
3751 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK		0x00001000
3757 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK		0x0000c000
3764 #define REG_A6XX_RB_SRGB_CNTL					0x0000880f
3765 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0				0x00000001
3766 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1				0x00000002
3767 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2				0x00000004
3768 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3				0x00000008
3769 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4				0x00000010
3770 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5				0x00000020
3771 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6				0x00000040
3772 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7				0x00000080
3774 #define REG_A6XX_RB_SAMPLE_CNTL					0x00008810
3775 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001
3777 #define REG_A6XX_RB_UNKNOWN_8811				0x00008811
3779 #define REG_A6XX_RB_UNKNOWN_8818				0x00008818
3781 #define REG_A6XX_RB_UNKNOWN_8819				0x00008819
3783 #define REG_A6XX_RB_UNKNOWN_881A				0x0000881a
3785 #define REG_A6XX_RB_UNKNOWN_881B				0x0000881b
3787 #define REG_A6XX_RB_UNKNOWN_881C				0x0000881c
3789 #define REG_A6XX_RB_UNKNOWN_881D				0x0000881d
3791 #define REG_A6XX_RB_UNKNOWN_881E				0x0000881e
3793 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }  in REG_A6XX_RB_MRT()
3795 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }  in REG_A6XX_RB_MRT_CONTROL()
3796 #define A6XX_RB_MRT_CONTROL_BLEND				0x00000001
3797 #define A6XX_RB_MRT_CONTROL_BLEND2				0x00000002
3798 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE				0x00000004
3799 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000078
3805 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x00000780
3812 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }  in REG_A6XX_RB_MRT_BLEND_CONTROL()
3813 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
3814 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
3819 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
3825 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
3831 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
3837 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
3843 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
3850 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }  in REG_A6XX_RB_MRT_BUF_INFO()
3851 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x000000ff
3852 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
3857 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x00000300
3863 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK			0x00000400
3869 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00006000
3876 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }  in REG_A6XX_RB_MRT_PITCH()
3877 #define A6XX_RB_MRT_PITCH__MASK					0x0000ffff
3878 #define A6XX_RB_MRT_PITCH__SHIFT				0
3884 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }  in REG_A6XX_RB_MRT_ARRAY_PITCH()
3885 #define A6XX_RB_MRT_ARRAY_PITCH__MASK				0x1fffffff
3886 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT				0
3892 static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }  in REG_A6XX_RB_MRT_BASE_LO()
3894 static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }  in REG_A6XX_RB_MRT_BASE_HI()
3896 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }  in REG_A6XX_RB_MRT_BASE()
3897 #define A6XX_RB_MRT_BASE__MASK					0xffffffff
3898 #define A6XX_RB_MRT_BASE__SHIFT					0
3904 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }  in REG_A6XX_RB_MRT_BASE_GMEM()
3905 #define A6XX_RB_MRT_BASE_GMEM__MASK				0xfffff000
3912 #define REG_A6XX_RB_BLEND_RED_F32				0x00008860
3913 #define A6XX_RB_BLEND_RED_F32__MASK				0xffffffff
3914 #define A6XX_RB_BLEND_RED_F32__SHIFT				0
3920 #define REG_A6XX_RB_BLEND_GREEN_F32				0x00008861
3921 #define A6XX_RB_BLEND_GREEN_F32__MASK				0xffffffff
3922 #define A6XX_RB_BLEND_GREEN_F32__SHIFT				0
3928 #define REG_A6XX_RB_BLEND_BLUE_F32				0x00008862
3929 #define A6XX_RB_BLEND_BLUE_F32__MASK				0xffffffff
3930 #define A6XX_RB_BLEND_BLUE_F32__SHIFT				0
3936 #define REG_A6XX_RB_BLEND_ALPHA_F32				0x00008863
3937 #define A6XX_RB_BLEND_ALPHA_F32__MASK				0xffffffff
3938 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT				0
3944 #define REG_A6XX_RB_ALPHA_CONTROL				0x00008864
3945 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK			0x000000ff
3946 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT			0
3951 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST			0x00000100
3952 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK		0x00000e00
3959 #define REG_A6XX_RB_BLEND_CNTL					0x00008865
3960 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
3961 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
3966 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND			0x00000100
3967 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
3968 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
3969 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE				0x00000800
3970 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK			0xffff0000
3977 #define REG_A6XX_RB_DEPTH_PLANE_CNTL				0x00008870
3978 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK			0x00000003
3979 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT			0
3985 #define REG_A6XX_RB_DEPTH_CNTL					0x00008871
3986 #define A6XX_RB_DEPTH_CNTL_Z_ENABLE				0x00000001
3987 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE			0x00000002
3988 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK				0x0000001c
3994 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE			0x00000020
3995 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE			0x00000040
3996 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE			0x00000080
3998 #define REG_A6XX_RB_DEPTH_BUFFER_INFO				0x00008872
3999 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK		0x00000007
4000 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT		0
4005 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK			0x00000018
4012 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH				0x00008873
4013 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK			0x00003fff
4014 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT			0
4020 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH			0x00008874
4021 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK			0x0fffffff
4022 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT			0
4028 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO			0x00008875
4030 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI			0x00008876
4032 #define REG_A6XX_RB_DEPTH_BUFFER_BASE				0x00008875
4033 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK				0xffffffff
4034 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT			0
4040 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM			0x00008877
4041 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK			0xfffff000
4048 #define REG_A6XX_RB_Z_BOUNDS_MIN				0x00008878
4049 #define A6XX_RB_Z_BOUNDS_MIN__MASK				0xffffffff
4050 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT				0
4056 #define REG_A6XX_RB_Z_BOUNDS_MAX				0x00008879
4057 #define A6XX_RB_Z_BOUNDS_MAX__MASK				0xffffffff
4058 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT				0
4064 #define REG_A6XX_RB_STENCIL_CONTROL				0x00008880
4065 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
4066 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
4067 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
4068 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
4074 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
4080 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
4086 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
4092 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
4098 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
4104 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
4110 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
4117 #define REG_A6XX_RB_STENCIL_INFO				0x00008881
4118 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
4119 #define A6XX_RB_STENCIL_INFO_UNK1				0x00000002
4121 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH			0x00008882
4122 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK			0x00000fff
4123 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT			0
4129 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH			0x00008883
4130 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK		0x00ffffff
4131 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT		0
4137 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO			0x00008884
4139 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI			0x00008885
4141 #define REG_A6XX_RB_STENCIL_BUFFER_BASE				0x00008884
4142 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK			0xffffffff
4143 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT			0
4149 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM			0x00008886
4150 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK			0xfffff000
4157 #define REG_A6XX_RB_STENCILREF					0x00008887
4158 #define A6XX_RB_STENCILREF_REF__MASK				0x000000ff
4159 #define A6XX_RB_STENCILREF_REF__SHIFT				0
4164 #define A6XX_RB_STENCILREF_BFREF__MASK				0x0000ff00
4171 #define REG_A6XX_RB_STENCILMASK					0x00008888
4172 #define A6XX_RB_STENCILMASK_MASK__MASK				0x000000ff
4173 #define A6XX_RB_STENCILMASK_MASK__SHIFT				0
4178 #define A6XX_RB_STENCILMASK_BFMASK__MASK			0x0000ff00
4185 #define REG_A6XX_RB_STENCILWRMASK				0x00008889
4186 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK			0x000000ff
4187 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT			0
4192 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK			0x0000ff00
4199 #define REG_A6XX_RB_WINDOW_OFFSET				0x00008890
4200 #define A6XX_RB_WINDOW_OFFSET_X__MASK				0x00003fff
4201 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT				0
4206 #define A6XX_RB_WINDOW_OFFSET_Y__MASK				0x3fff0000
4213 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL			0x00008891
4214 #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0			0x00000001
4215 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
4217 #define REG_A6XX_RB_LRZ_CNTL					0x00008898
4218 #define A6XX_RB_LRZ_CNTL_ENABLE					0x00000001
4220 #define REG_A6XX_RB_Z_CLAMP_MIN					0x000088c0
4221 #define A6XX_RB_Z_CLAMP_MIN__MASK				0xffffffff
4222 #define A6XX_RB_Z_CLAMP_MIN__SHIFT				0
4228 #define REG_A6XX_RB_Z_CLAMP_MAX					0x000088c1
4229 #define A6XX_RB_Z_CLAMP_MAX__MASK				0xffffffff
4230 #define A6XX_RB_Z_CLAMP_MAX__SHIFT				0
4236 #define REG_A6XX_RB_UNKNOWN_88D0				0x000088d0
4237 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK				0x00001fff
4238 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT			0
4243 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK			0x07ff0000
4250 #define REG_A6XX_RB_BLIT_SCISSOR_TL				0x000088d1
4251 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK				0x00003fff
4252 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT			0
4257 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK				0x3fff0000
4264 #define REG_A6XX_RB_BLIT_SCISSOR_BR				0x000088d2
4265 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK				0x00003fff
4266 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT			0
4271 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK				0x3fff0000
4278 #define REG_A6XX_RB_BIN_CONTROL2				0x000088d3
4279 #define A6XX_RB_BIN_CONTROL2_BINW__MASK				0x0000003f
4280 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT			0
4285 #define A6XX_RB_BIN_CONTROL2_BINH__MASK				0x00007f00
4292 #define REG_A6XX_RB_WINDOW_OFFSET2				0x000088d4
4293 #define A6XX_RB_WINDOW_OFFSET2_X__MASK				0x00003fff
4294 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT				0
4299 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK				0x3fff0000
4306 #define REG_A6XX_RB_MSAA_CNTL					0x000088d5
4307 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK				0x00000018
4314 #define REG_A6XX_RB_BLIT_BASE_GMEM				0x000088d6
4315 #define A6XX_RB_BLIT_BASE_GMEM__MASK				0xfffff000
4322 #define REG_A6XX_RB_BLIT_DST_INFO				0x000088d7
4323 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK			0x00000003
4324 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT			0
4329 #define A6XX_RB_BLIT_DST_INFO_FLAGS				0x00000004
4330 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK			0x00000018
4336 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK			0x00000060
4342 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK		0x00007f80
4348 #define A6XX_RB_BLIT_DST_INFO_UNK15				0x00008000
4350 #define REG_A6XX_RB_BLIT_DST					0x000088d8
4351 #define A6XX_RB_BLIT_DST__MASK					0xffffffff
4352 #define A6XX_RB_BLIT_DST__SHIFT					0
4358 #define REG_A6XX_RB_BLIT_DST_LO					0x000088d8
4360 #define REG_A6XX_RB_BLIT_DST_HI					0x000088d9
4362 #define REG_A6XX_RB_BLIT_DST_PITCH				0x000088da
4363 #define A6XX_RB_BLIT_DST_PITCH__MASK				0x0000ffff
4364 #define A6XX_RB_BLIT_DST_PITCH__SHIFT				0
4370 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH			0x000088db
4371 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK			0x1fffffff
4372 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT			0
4378 #define REG_A6XX_RB_BLIT_FLAG_DST				0x000088dc
4379 #define A6XX_RB_BLIT_FLAG_DST__MASK				0xffffffff
4380 #define A6XX_RB_BLIT_FLAG_DST__SHIFT				0
4386 #define REG_A6XX_RB_BLIT_FLAG_DST_LO				0x000088dc
4388 #define REG_A6XX_RB_BLIT_FLAG_DST_HI				0x000088dd
4390 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH				0x000088de
4391 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK			0x000007ff
4392 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT		0
4397 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK		0x0ffff800
4404 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0			0x000088df
4406 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1			0x000088e0
4408 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2			0x000088e1
4410 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3			0x000088e2
4412 #define REG_A6XX_RB_BLIT_INFO					0x000088e3
4413 #define A6XX_RB_BLIT_INFO_UNK0					0x00000001
4414 #define A6XX_RB_BLIT_INFO_GMEM					0x00000002
4415 #define A6XX_RB_BLIT_INFO_INTEGER				0x00000004
4416 #define A6XX_RB_BLIT_INFO_DEPTH					0x00000008
4417 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK			0x000000f0
4423 #define A6XX_RB_BLIT_INFO_UNK8__MASK				0x00000300
4429 #define A6XX_RB_BLIT_INFO_UNK12__MASK				0x0000f000
4436 #define REG_A6XX_RB_UNKNOWN_88F0				0x000088f0
4438 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE			0x000088f1
4439 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK			0xffffffff
4440 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT			0
4446 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH			0x000088f3
4447 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
4448 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
4453 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x00fff800
4460 #define REG_A6XX_RB_UNKNOWN_88F4				0x000088f4
4462 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO			0x00008900
4464 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI			0x00008901
4466 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE			0x00008900
4467 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK			0xffffffff
4468 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT			0
4474 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH			0x00008902
4475 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK		0x0000007f
4476 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
4481 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK		0x00000700
4487 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK	0x0ffff800
4494 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }  in REG_A6XX_RB_MRT_FLAG_BUFFER()
4496 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i…  in REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO()
4498 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i…  in REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI()
4500 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }  in REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR()
4501 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK			0xffffffff
4502 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT			0
4508 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0;…  in REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH()
4509 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
4510 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
4515 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffff800
4522 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO			0x00008927
4524 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI			0x00008928
4526 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR				0x00008927
4527 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK				0xffffffff
4528 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT			0
4534 #define REG_A6XX_RB_2D_BLIT_CNTL				0x00008c00
4535 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
4536 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT			0
4541 #define A6XX_RB_2D_BLIT_CNTL_UNK3__MASK				0x00000078
4547 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
4548 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK			0x0000ff00
4554 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR				0x00010000
4555 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK			0x00060000
4561 #define A6XX_RB_2D_BLIT_CNTL_D24S8				0x00080000
4562 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK				0x00f00000
4568 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK				0x1f000000
4574 #define A6XX_RB_2D_BLIT_CNTL_UNK29__MASK			0x20000000
4581 #define REG_A6XX_RB_2D_UNKNOWN_8C01				0x00008c01
4583 #define REG_A6XX_RB_2D_DST_INFO					0x00008c17
4584 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK			0x000000ff
4585 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT			0
4590 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK			0x00000300
4596 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK			0x00000c00
4602 #define A6XX_RB_2D_DST_INFO_FLAGS				0x00001000
4603 #define A6XX_RB_2D_DST_INFO_SRGB				0x00002000
4604 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK			0x0000c000
4610 #define A6XX_RB_2D_DST_INFO_FILTER				0x00010000
4611 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE			0x00040000
4612 #define A6XX_RB_2D_DST_INFO_UNK20				0x00100000
4613 #define A6XX_RB_2D_DST_INFO_UNK22				0x00400000
4615 #define REG_A6XX_RB_2D_DST_LO					0x00008c18
4617 #define REG_A6XX_RB_2D_DST_HI					0x00008c19
4619 #define REG_A6XX_RB_2D_DST					0x00008c18
4620 #define A6XX_RB_2D_DST__MASK					0xffffffff
4621 #define A6XX_RB_2D_DST__SHIFT					0
4627 #define REG_A6XX_RB_2D_DST_PITCH				0x00008c1a
4628 #define A6XX_RB_2D_DST_PITCH__MASK				0x0000ffff
4629 #define A6XX_RB_2D_DST_PITCH__SHIFT				0
4635 #define REG_A6XX_RB_2D_DST_PLANE1				0x00008c1b
4636 #define A6XX_RB_2D_DST_PLANE1__MASK				0xffffffff
4637 #define A6XX_RB_2D_DST_PLANE1__SHIFT				0
4643 #define REG_A6XX_RB_2D_DST_PLANE_PITCH				0x00008c1d
4644 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK			0x0000ffff
4645 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT			0
4651 #define REG_A6XX_RB_2D_DST_PLANE2				0x00008c1e
4652 #define A6XX_RB_2D_DST_PLANE2__MASK				0xffffffff
4653 #define A6XX_RB_2D_DST_PLANE2__SHIFT				0
4659 #define REG_A6XX_RB_2D_DST_FLAGS_LO				0x00008c20
4661 #define REG_A6XX_RB_2D_DST_FLAGS_HI				0x00008c21
4663 #define REG_A6XX_RB_2D_DST_FLAGS				0x00008c20
4664 #define A6XX_RB_2D_DST_FLAGS__MASK				0xffffffff
4665 #define A6XX_RB_2D_DST_FLAGS__SHIFT				0
4671 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH				0x00008c22
4672 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK			0x000000ff
4673 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT			0
4679 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE				0x00008c23
4680 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK			0xffffffff
4681 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT			0
4687 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH			0x00008c25
4688 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK			0x000000ff
4689 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT			0
4695 #define REG_A6XX_RB_2D_SRC_SOLID_C0				0x00008c2c
4697 #define REG_A6XX_RB_2D_SRC_SOLID_C1				0x00008c2d
4699 #define REG_A6XX_RB_2D_SRC_SOLID_C2				0x00008c2e
4701 #define REG_A6XX_RB_2D_SRC_SOLID_C3				0x00008c2f
4703 #define REG_A6XX_RB_UNKNOWN_8E01				0x00008e01
4705 #define REG_A6XX_RB_UNKNOWN_8E04				0x00008e04
4707 #define REG_A6XX_RB_ADDR_MODE_CNTL				0x00008e05
4709 #define REG_A6XX_RB_CCU_CNTL					0x00008e07
4710 #define A6XX_RB_CCU_CNTL_OFFSET__MASK				0xff800000
4716 #define A6XX_RB_CCU_CNTL_GMEM					0x00400000
4717 #define A6XX_RB_CCU_CNTL_UNK2					0x00000004
4719 #define REG_A6XX_RB_NC_MODE_CNTL				0x00008e08
4720 #define A6XX_RB_NC_MODE_CNTL_MODE				0x00000001
4721 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK			0x00000006
4727 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH			0x00000008
4728 #define A6XX_RB_NC_MODE_CNTL_AMSBC				0x00000010
4729 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK			0x00000400
4735 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR			0x00000800
4736 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK			0x00003000
4743 #define REG_A6XX_RB_PERFCTR_RB_SEL_0				0x00008e10
4745 #define REG_A6XX_RB_PERFCTR_RB_SEL_1				0x00008e11
4747 #define REG_A6XX_RB_PERFCTR_RB_SEL_2				0x00008e12
4749 #define REG_A6XX_RB_PERFCTR_RB_SEL_3				0x00008e13
4751 #define REG_A6XX_RB_PERFCTR_RB_SEL_4				0x00008e14
4753 #define REG_A6XX_RB_PERFCTR_RB_SEL_5				0x00008e15
4755 #define REG_A6XX_RB_PERFCTR_RB_SEL_6				0x00008e16
4757 #define REG_A6XX_RB_PERFCTR_RB_SEL_7				0x00008e17
4759 #define REG_A6XX_RB_PERFCTR_CCU_SEL_0				0x00008e18
4761 #define REG_A6XX_RB_PERFCTR_CCU_SEL_1				0x00008e19
4763 #define REG_A6XX_RB_PERFCTR_CCU_SEL_2				0x00008e1a
4765 #define REG_A6XX_RB_PERFCTR_CCU_SEL_3				0x00008e1b
4767 #define REG_A6XX_RB_PERFCTR_CCU_SEL_4				0x00008e1c
4769 #define REG_A6XX_RB_UNKNOWN_8E28				0x00008e28
4771 #define REG_A6XX_RB_PERFCTR_CMP_SEL_0				0x00008e2c
4773 #define REG_A6XX_RB_PERFCTR_CMP_SEL_1				0x00008e2d
4775 #define REG_A6XX_RB_PERFCTR_CMP_SEL_2				0x00008e2e
4777 #define REG_A6XX_RB_PERFCTR_CMP_SEL_3				0x00008e2f
4779 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST			0x00008e3b
4781 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD			0x00008e3d
4783 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE		0x00008e50
4785 #define REG_A6XX_RB_UNKNOWN_8E51				0x00008e51
4786 #define A6XX_RB_UNKNOWN_8E51__MASK				0xffffffff
4787 #define A6XX_RB_UNKNOWN_8E51__SHIFT				0
4793 #define REG_A6XX_VPC_UNKNOWN_9100				0x00009100
4795 #define REG_A6XX_VPC_VS_CLIP_CNTL				0x00009101
4796 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4797 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4802 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4808 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4815 #define REG_A6XX_VPC_GS_CLIP_CNTL				0x00009102
4816 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4817 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4822 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4828 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4835 #define REG_A6XX_VPC_DS_CLIP_CNTL				0x00009103
4836 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4837 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4842 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4848 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4855 #define REG_A6XX_VPC_VS_LAYER_CNTL				0x00009104
4856 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4857 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT			0
4862 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4869 #define REG_A6XX_VPC_GS_LAYER_CNTL				0x00009105
4870 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4871 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT			0
4876 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4883 #define REG_A6XX_VPC_DS_LAYER_CNTL				0x00009106
4884 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4885 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT			0
4890 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4897 #define REG_A6XX_VPC_UNKNOWN_9107				0x00009107
4899 #define REG_A6XX_VPC_POLYGON_MODE				0x00009108
4900 #define A6XX_VPC_POLYGON_MODE_MODE__MASK			0x00000003
4901 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT			0
4907 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_INTERP()
4909 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_INTERP_MODE()
4911 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_PS_REPL()
4913 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0;…  in REG_A6XX_VPC_VARYING_PS_REPL_MODE()
4915 #define REG_A6XX_VPC_UNKNOWN_9210				0x00009210
4917 #define REG_A6XX_VPC_UNKNOWN_9211				0x00009211
4919 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }  in REG_A6XX_VPC_VAR()
4921 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }  in REG_A6XX_VPC_VAR_DISABLE()
4923 #define REG_A6XX_VPC_SO_CNTL					0x00009216
4924 #define A6XX_VPC_SO_CNTL_UNK0__MASK				0x000000ff
4925 #define A6XX_VPC_SO_CNTL_UNK0__SHIFT				0
4930 #define A6XX_VPC_SO_CNTL_ENABLE					0x00010000
4932 #define REG_A6XX_VPC_SO_PROG					0x00009217
4933 #define A6XX_VPC_SO_PROG_A_BUF__MASK				0x00000003
4934 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT				0
4939 #define A6XX_VPC_SO_PROG_A_OFF__MASK				0x000007fc
4945 #define A6XX_VPC_SO_PROG_A_EN					0x00000800
4946 #define A6XX_VPC_SO_PROG_B_BUF__MASK				0x00003000
4952 #define A6XX_VPC_SO_PROG_B_OFF__MASK				0x007fc000
4958 #define A6XX_VPC_SO_PROG_B_EN					0x00800000
4960 #define REG_A6XX_VPC_SO_STREAM_COUNTS_LO			0x00009218
4962 #define REG_A6XX_VPC_SO_STREAM_COUNTS_HI			0x00009219
4964 #define REG_A6XX_VPC_SO_STREAM_COUNTS				0x00009218
4965 #define A6XX_VPC_SO_STREAM_COUNTS__MASK				0xffffffff
4966 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT			0
4972 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }  in REG_A6XX_VPC_SO()
4974 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_BASE()
4975 #define A6XX_VPC_SO_BUFFER_BASE__MASK				0xffffffff
4976 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT				0
4982 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_BASE_LO()
4984 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_BASE_HI()
4986 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_SIZE()
4987 #define A6XX_VPC_SO_BUFFER_SIZE__MASK				0xfffffffc
4994 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }  in REG_A6XX_VPC_SO_NCOMP()
4996 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_OFFSET()
4997 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK				0xfffffffc
5004 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }  in REG_A6XX_VPC_SO_FLUSH_BASE()
5005 #define A6XX_VPC_SO_FLUSH_BASE__MASK				0xffffffff
5006 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT				0
5012 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }  in REG_A6XX_VPC_SO_FLUSH_BASE_LO()
5014 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }  in REG_A6XX_VPC_SO_FLUSH_BASE_HI()
5016 #define REG_A6XX_VPC_POINT_COORD_INVERT				0x00009236
5017 #define A6XX_VPC_POINT_COORD_INVERT_INVERT			0x00000001
5019 #define REG_A6XX_VPC_UNKNOWN_9300				0x00009300
5021 #define REG_A6XX_VPC_VS_PACK					0x00009301
5022 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
5023 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT			0
5028 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK			0x0000ff00
5034 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK				0x00ff0000
5040 #define A6XX_VPC_VS_PACK_UNK24__MASK				0x0f000000
5047 #define REG_A6XX_VPC_GS_PACK					0x00009302
5048 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
5049 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT			0
5054 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK			0x0000ff00
5060 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK				0x00ff0000
5066 #define A6XX_VPC_GS_PACK_UNK24__MASK				0x0f000000
5073 #define REG_A6XX_VPC_DS_PACK					0x00009303
5074 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
5075 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT			0
5080 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK			0x0000ff00
5086 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK				0x00ff0000
5092 #define A6XX_VPC_DS_PACK_UNK24__MASK				0x0f000000
5099 #define REG_A6XX_VPC_CNTL_0					0x00009304
5100 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK			0x000000ff
5101 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT			0
5106 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK				0x0000ff00
5112 #define A6XX_VPC_CNTL_0_VARYING					0x00010000
5113 #define A6XX_VPC_CNTL_0_UNKLOC__MASK				0xff000000
5120 #define REG_A6XX_VPC_SO_BUF_CNTL				0x00009305
5121 #define A6XX_VPC_SO_BUF_CNTL_BUF0				0x00000001
5122 #define A6XX_VPC_SO_BUF_CNTL_BUF1				0x00000008
5123 #define A6XX_VPC_SO_BUF_CNTL_BUF2				0x00000040
5124 #define A6XX_VPC_SO_BUF_CNTL_BUF3				0x00000200
5125 #define A6XX_VPC_SO_BUF_CNTL_ENABLE				0x00008000
5126 #define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK			0x000f0000
5133 #define REG_A6XX_VPC_SO_DISABLE					0x00009306
5134 #define A6XX_VPC_SO_DISABLE_DISABLE				0x00000001
5136 #define REG_A6XX_VPC_UNKNOWN_9600				0x00009600
5138 #define REG_A6XX_VPC_ADDR_MODE_CNTL				0x00009601
5140 #define REG_A6XX_VPC_UNKNOWN_9602				0x00009602
5142 #define REG_A6XX_VPC_UNKNOWN_9603				0x00009603
5144 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0				0x00009604
5146 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1				0x00009605
5148 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2				0x00009606
5150 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3				0x00009607
5152 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4				0x00009608
5154 #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5				0x00009609
5156 #define REG_A6XX_PC_TESS_NUM_VERTEX				0x00009800
5158 #define REG_A6XX_PC_UNKNOWN_9801				0x00009801
5159 #define A6XX_PC_UNKNOWN_9801_UNK0__MASK				0x000007ff
5160 #define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT			0
5165 #define A6XX_PC_UNKNOWN_9801_UNK13__MASK			0x00002000
5172 #define REG_A6XX_PC_TESS_CNTL					0x00009802
5173 #define A6XX_PC_TESS_CNTL_SPACING__MASK				0x00000003
5174 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT			0
5179 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK				0x0000000c
5186 #define REG_A6XX_PC_RESTART_INDEX				0x00009803
5188 #define REG_A6XX_PC_MODE_CNTL					0x00009804
5190 #define REG_A6XX_PC_UNKNOWN_9805				0x00009805
5192 #define REG_A6XX_PC_PRIMID_PASSTHRU				0x00009806
5194 #define REG_A6XX_PC_DRAW_CMD					0x00009840
5195 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK				0x000000ff
5196 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT			0
5202 #define REG_A6XX_PC_DISPATCH_CMD				0x00009841
5203 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
5204 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT			0
5210 #define REG_A6XX_PC_EVENT_CMD					0x00009842
5211 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK			0x00ff0000
5217 #define A6XX_PC_EVENT_CMD_EVENT__MASK				0x0000007f
5218 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT				0
5224 #define REG_A6XX_PC_POLYGON_MODE				0x00009981
5225 #define A6XX_PC_POLYGON_MODE_MODE__MASK				0x00000003
5226 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT			0
5232 #define REG_A6XX_PC_UNKNOWN_9980				0x00009980
5234 #define REG_A6XX_PC_PRIMITIVE_CNTL_0				0x00009b00
5235 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART		0x00000001
5236 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST		0x00000002
5237 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN	0x00000004
5238 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3				0x00000008
5240 #define REG_A6XX_PC_VS_OUT_CNTL					0x00009b01
5241 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5242 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5247 #define A6XX_PC_VS_OUT_CNTL_PSIZE				0x00000100
5248 #define A6XX_PC_VS_OUT_CNTL_LAYER				0x00000200
5249 #define A6XX_PC_VS_OUT_CNTL_VIEW				0x00000400
5250 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5251 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5258 #define REG_A6XX_PC_GS_OUT_CNTL					0x00009b02
5259 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5260 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5265 #define A6XX_PC_GS_OUT_CNTL_PSIZE				0x00000100
5266 #define A6XX_PC_GS_OUT_CNTL_LAYER				0x00000200
5267 #define A6XX_PC_GS_OUT_CNTL_VIEW				0x00000400
5268 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5269 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5276 #define REG_A6XX_PC_PRIMITIVE_CNTL_3				0x00009b03
5278 #define REG_A6XX_PC_DS_OUT_CNTL					0x00009b04
5279 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
5280 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
5285 #define A6XX_PC_DS_OUT_CNTL_PSIZE				0x00000100
5286 #define A6XX_PC_DS_OUT_CNTL_LAYER				0x00000200
5287 #define A6XX_PC_DS_OUT_CNTL_VIEW				0x00000400
5288 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID			0x00000800
5289 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
5296 #define REG_A6XX_PC_PRIMITIVE_CNTL_5				0x00009b05
5297 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK		0x000000ff
5298 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT		0
5303 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK		0x00007c00
5309 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK		0x00030000
5315 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK			0x00040000
5322 #define REG_A6XX_PC_PRIMITIVE_CNTL_6				0x00009b06
5323 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK		0x000007ff
5324 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT		0
5330 #define REG_A6XX_PC_UNKNOWN_9B07				0x00009b07
5332 #define REG_A6XX_PC_UNKNOWN_9B08				0x00009b08
5334 #define REG_A6XX_PC_2D_EVENT_CMD				0x00009c00
5335 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK			0x0000007f
5336 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT			0
5341 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
5348 #define REG_A6XX_PC_DBG_ECO_CNTL				0x00009e00
5350 #define REG_A6XX_PC_ADDR_MODE_CNTL				0x00009e01
5352 #define REG_A6XX_PC_TESSFACTOR_ADDR_LO				0x00009e08
5354 #define REG_A6XX_PC_TESSFACTOR_ADDR_HI				0x00009e09
5356 #define REG_A6XX_PC_TESSFACTOR_ADDR				0x00009e08
5357 #define A6XX_PC_TESSFACTOR_ADDR__MASK				0xffffffff
5358 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT				0
5364 #define REG_A6XX_PC_VSTREAM_CONTROL				0x00009e11
5365 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK			0x0000ffff
5366 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT			0
5371 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK			0x003f0000
5377 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK			0x07c00000
5384 #define REG_A6XX_PC_BIN_PRIM_STRM				0x00009e12
5385 #define A6XX_PC_BIN_PRIM_STRM__MASK				0xffffffff
5386 #define A6XX_PC_BIN_PRIM_STRM__SHIFT				0
5392 #define REG_A6XX_PC_BIN_DRAW_STRM				0x00009e14
5393 #define A6XX_PC_BIN_DRAW_STRM__MASK				0xffffffff
5394 #define A6XX_PC_BIN_DRAW_STRM__SHIFT				0
5400 #define REG_A6XX_PC_PERFCTR_PC_SEL_0				0x00009e34
5402 #define REG_A6XX_PC_PERFCTR_PC_SEL_1				0x00009e35
5404 #define REG_A6XX_PC_PERFCTR_PC_SEL_2				0x00009e36
5406 #define REG_A6XX_PC_PERFCTR_PC_SEL_3				0x00009e37
5408 #define REG_A6XX_PC_PERFCTR_PC_SEL_4				0x00009e38
5410 #define REG_A6XX_PC_PERFCTR_PC_SEL_5				0x00009e39
5412 #define REG_A6XX_PC_PERFCTR_PC_SEL_6				0x00009e3a
5414 #define REG_A6XX_PC_PERFCTR_PC_SEL_7				0x00009e3b
5416 #define REG_A6XX_PC_UNKNOWN_9E72				0x00009e72
5418 #define REG_A6XX_VFD_CONTROL_0					0x0000a000
5419 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK			0x0000003f
5420 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT			0
5425 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK			0x00003f00
5432 #define REG_A6XX_VFD_CONTROL_1					0x0000a001
5433 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK			0x000000ff
5434 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT			0
5439 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK			0x0000ff00
5445 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK			0x00ff0000
5452 #define REG_A6XX_VFD_CONTROL_2					0x0000a002
5453 #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK		0x000000ff
5454 #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT		0
5459 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK		0x0000ff00
5466 #define REG_A6XX_VFD_CONTROL_3					0x0000a003
5467 #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK		0x0000ff00
5473 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
5479 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000
5486 #define REG_A6XX_VFD_CONTROL_4					0x0000a004
5488 #define REG_A6XX_VFD_CONTROL_5					0x0000a005
5489 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK			0x000000ff
5490 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT		0
5496 #define REG_A6XX_VFD_CONTROL_6					0x0000a006
5497 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU			0x00000001
5499 #define REG_A6XX_VFD_MODE_CNTL					0x0000a007
5500 #define A6XX_VFD_MODE_CNTL_BINNING_PASS				0x00000001
5502 #define REG_A6XX_VFD_UNKNOWN_A008				0x0000a008
5504 #define REG_A6XX_VFD_ADD_OFFSET					0x0000a009
5505 #define A6XX_VFD_ADD_OFFSET_VERTEX				0x00000001
5506 #define A6XX_VFD_ADD_OFFSET_INSTANCE				0x00000002
5508 #define REG_A6XX_VFD_INDEX_OFFSET				0x0000a00e
5510 #define REG_A6XX_VFD_INSTANCE_START_OFFSET			0x0000a00f
5512 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }  in REG_A6XX_VFD_FETCH()
5514 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_BASE()
5516 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_BASE_LO()
5518 static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_BASE_HI()
5520 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_SIZE()
5522 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_STRIDE()
5524 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }  in REG_A6XX_VFD_DECODE()
5526 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }  in REG_A6XX_VFD_DECODE_INSTR()
5527 #define A6XX_VFD_DECODE_INSTR_IDX__MASK				0x0000001f
5528 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT			0
5533 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK			0x0001ffe0
5539 #define A6XX_VFD_DECODE_INSTR_INSTANCED				0x00020000
5540 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK			0x0ff00000
5546 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK			0x30000000
5552 #define A6XX_VFD_DECODE_INSTR_UNK30				0x40000000
5553 #define A6XX_VFD_DECODE_INSTR_FLOAT				0x80000000
5555 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }  in REG_A6XX_VFD_DECODE_STEP_RATE()
5557 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }  in REG_A6XX_VFD_DEST_CNTL()
5559 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }  in REG_A6XX_VFD_DEST_CNTL_INSTR()
5560 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK		0x0000000f
5561 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT		0
5566 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK			0x00000ff0
5573 #define REG_A6XX_SP_UNKNOWN_A0F8				0x0000a0f8
5575 #define REG_A6XX_SP_VS_CTRL_REG0				0x0000a800
5576 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5582 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5588 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5594 #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00100000
5600 #define A6XX_SP_VS_CTRL_REG0_VARYING				0x00400000
5601 #define A6XX_SP_VS_CTRL_REG0_DIFF_FINE				0x00800000
5602 #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x04000000
5603 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS				0x80000000
5605 #define REG_A6XX_SP_VS_BRANCH_COND				0x0000a801
5607 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL				0x0000a802
5608 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5609 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT			0
5615 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }  in REG_A6XX_SP_VS_OUT()
5617 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }  in REG_A6XX_SP_VS_OUT_REG()
5618 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
5619 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
5624 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5630 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK			0x00ff0000
5636 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5643 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }  in REG_A6XX_SP_VS_VPC_DST()
5645 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }  in REG_A6XX_SP_VS_VPC_DST_REG()
5646 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5647 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
5652 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5658 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5664 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
5671 #define REG_A6XX_SP_UNKNOWN_A81B				0x0000a81b
5673 #define REG_A6XX_SP_VS_OBJ_START_LO				0x0000a81c
5675 #define REG_A6XX_SP_VS_OBJ_START_HI				0x0000a81d
5677 #define REG_A6XX_SP_VS_TEX_COUNT				0x0000a822
5679 #define REG_A6XX_SP_VS_CONFIG					0x0000a823
5680 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX				0x00000001
5681 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP				0x00000002
5682 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO				0x00000004
5683 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO				0x00000008
5684 #define A6XX_SP_VS_CONFIG_ENABLED				0x00000100
5685 #define A6XX_SP_VS_CONFIG_NTEX__MASK				0x0001fe00
5691 #define A6XX_SP_VS_CONFIG_NSAMP__MASK				0x003e0000
5697 #define A6XX_SP_VS_CONFIG_NIBO__MASK				0x3fc00000
5704 #define REG_A6XX_SP_VS_INSTRLEN					0x0000a824
5706 #define REG_A6XX_SP_HS_CTRL_REG0				0x0000a830
5707 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5713 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5719 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5725 #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK			0x00100000
5731 #define A6XX_SP_HS_CTRL_REG0_VARYING				0x00400000
5732 #define A6XX_SP_HS_CTRL_REG0_DIFF_FINE				0x00800000
5733 #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE			0x04000000
5734 #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS				0x80000000
5736 #define REG_A6XX_SP_HS_UNKNOWN_A831				0x0000a831
5738 #define REG_A6XX_SP_HS_UNKNOWN_A833				0x0000a833
5740 #define REG_A6XX_SP_HS_OBJ_START_LO				0x0000a834
5742 #define REG_A6XX_SP_HS_OBJ_START_HI				0x0000a835
5744 #define REG_A6XX_SP_HS_TEX_COUNT				0x0000a83a
5746 #define REG_A6XX_SP_HS_CONFIG					0x0000a83b
5747 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX				0x00000001
5748 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP				0x00000002
5749 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO				0x00000004
5750 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO				0x00000008
5751 #define A6XX_SP_HS_CONFIG_ENABLED				0x00000100
5752 #define A6XX_SP_HS_CONFIG_NTEX__MASK				0x0001fe00
5758 #define A6XX_SP_HS_CONFIG_NSAMP__MASK				0x003e0000
5764 #define A6XX_SP_HS_CONFIG_NIBO__MASK				0x3fc00000
5771 #define REG_A6XX_SP_HS_INSTRLEN					0x0000a83c
5773 #define REG_A6XX_SP_DS_CTRL_REG0				0x0000a840
5774 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5780 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5786 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5792 #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK			0x00100000
5798 #define A6XX_SP_DS_CTRL_REG0_VARYING				0x00400000
5799 #define A6XX_SP_DS_CTRL_REG0_DIFF_FINE				0x00800000
5800 #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE			0x04000000
5801 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS				0x80000000
5803 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL				0x0000a842
5804 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5805 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT			0
5811 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }  in REG_A6XX_SP_DS_OUT()
5813 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }  in REG_A6XX_SP_DS_OUT_REG()
5814 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK			0x000000ff
5815 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT			0
5820 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5826 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK			0x00ff0000
5832 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5839 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }  in REG_A6XX_SP_DS_VPC_DST()
5841 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }  in REG_A6XX_SP_DS_VPC_DST_REG()
5842 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5843 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT			0
5848 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5854 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5860 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
5867 #define REG_A6XX_SP_DS_UNKNOWN_A85B				0x0000a85b
5869 #define REG_A6XX_SP_DS_OBJ_START_LO				0x0000a85c
5871 #define REG_A6XX_SP_DS_OBJ_START_HI				0x0000a85d
5873 #define REG_A6XX_SP_DS_TEX_COUNT				0x0000a862
5875 #define REG_A6XX_SP_DS_CONFIG					0x0000a863
5876 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX				0x00000001
5877 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP				0x00000002
5878 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO				0x00000004
5879 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO				0x00000008
5880 #define A6XX_SP_DS_CONFIG_ENABLED				0x00000100
5881 #define A6XX_SP_DS_CONFIG_NTEX__MASK				0x0001fe00
5887 #define A6XX_SP_DS_CONFIG_NSAMP__MASK				0x003e0000
5893 #define A6XX_SP_DS_CONFIG_NIBO__MASK				0x3fc00000
5900 #define REG_A6XX_SP_DS_INSTRLEN					0x0000a864
5902 #define REG_A6XX_SP_GS_CTRL_REG0				0x0000a870
5903 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5909 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5915 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5921 #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK			0x00100000
5927 #define A6XX_SP_GS_CTRL_REG0_VARYING				0x00400000
5928 #define A6XX_SP_GS_CTRL_REG0_DIFF_FINE				0x00800000
5929 #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE			0x04000000
5930 #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS				0x80000000
5932 #define REG_A6XX_SP_GS_PRIM_SIZE				0x0000a871
5934 #define REG_A6XX_SP_GS_BRANCH_COND				0x0000a872
5936 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL				0x0000a873
5937 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5938 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT			0
5943 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
5950 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }  in REG_A6XX_SP_GS_OUT()
5952 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }  in REG_A6XX_SP_GS_OUT_REG()
5953 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK			0x000000ff
5954 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT			0
5959 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5965 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK			0x00ff0000
5971 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5978 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }  in REG_A6XX_SP_GS_VPC_DST()
5980 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }  in REG_A6XX_SP_GS_VPC_DST_REG()
5981 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5982 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT			0
5987 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5993 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5999 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
6006 #define REG_A6XX_SP_GS_OBJ_START_LO				0x0000a88d
6008 #define REG_A6XX_SP_GS_OBJ_START_HI				0x0000a88e
6010 #define REG_A6XX_SP_GS_TEX_COUNT				0x0000a893
6012 #define REG_A6XX_SP_GS_CONFIG					0x0000a894
6013 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX				0x00000001
6014 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP				0x00000002
6015 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO				0x00000004
6016 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO				0x00000008
6017 #define A6XX_SP_GS_CONFIG_ENABLED				0x00000100
6018 #define A6XX_SP_GS_CONFIG_NTEX__MASK				0x0001fe00
6024 #define A6XX_SP_GS_CONFIG_NSAMP__MASK				0x003e0000
6030 #define A6XX_SP_GS_CONFIG_NIBO__MASK				0x3fc00000
6037 #define REG_A6XX_SP_GS_INSTRLEN					0x0000a895
6039 #define REG_A6XX_SP_VS_TEX_SAMP_LO				0x0000a8a0
6041 #define REG_A6XX_SP_VS_TEX_SAMP_HI				0x0000a8a1
6043 #define REG_A6XX_SP_HS_TEX_SAMP_LO				0x0000a8a2
6045 #define REG_A6XX_SP_HS_TEX_SAMP_HI				0x0000a8a3
6047 #define REG_A6XX_SP_DS_TEX_SAMP_LO				0x0000a8a4
6049 #define REG_A6XX_SP_DS_TEX_SAMP_HI				0x0000a8a5
6051 #define REG_A6XX_SP_GS_TEX_SAMP_LO				0x0000a8a6
6053 #define REG_A6XX_SP_GS_TEX_SAMP_HI				0x0000a8a7
6055 #define REG_A6XX_SP_VS_TEX_CONST_LO				0x0000a8a8
6057 #define REG_A6XX_SP_VS_TEX_CONST_HI				0x0000a8a9
6059 #define REG_A6XX_SP_HS_TEX_CONST_LO				0x0000a8aa
6061 #define REG_A6XX_SP_HS_TEX_CONST_HI				0x0000a8ab
6063 #define REG_A6XX_SP_DS_TEX_CONST_LO				0x0000a8ac
6065 #define REG_A6XX_SP_DS_TEX_CONST_HI				0x0000a8ad
6067 #define REG_A6XX_SP_GS_TEX_CONST_LO				0x0000a8ae
6069 #define REG_A6XX_SP_GS_TEX_CONST_HI				0x0000a8af
6071 #define REG_A6XX_SP_FS_CTRL_REG0				0x0000a980
6072 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
6078 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
6084 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
6090 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00100000
6096 #define A6XX_SP_FS_CTRL_REG0_VARYING				0x00400000
6097 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE				0x00800000
6098 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x04000000
6099 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS				0x80000000
6101 #define REG_A6XX_SP_FS_BRANCH_COND				0x0000a981
6103 #define REG_A6XX_SP_UNKNOWN_A982				0x0000a982
6105 #define REG_A6XX_SP_FS_OBJ_START_LO				0x0000a983
6107 #define REG_A6XX_SP_FS_OBJ_START_HI				0x0000a984
6109 #define REG_A6XX_SP_BLEND_CNTL					0x0000a989
6110 #define A6XX_SP_BLEND_CNTL_ENABLED				0x00000001
6111 #define A6XX_SP_BLEND_CNTL_UNK8					0x00000100
6112 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
6113 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
6115 #define REG_A6XX_SP_SRGB_CNTL					0x0000a98a
6116 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0				0x00000001
6117 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1				0x00000002
6118 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2				0x00000004
6119 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3				0x00000008
6120 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4				0x00000010
6121 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5				0x00000020
6122 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6				0x00000040
6123 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7				0x00000080
6125 #define REG_A6XX_SP_FS_RENDER_COMPONENTS			0x0000a98b
6126 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK			0x0000000f
6127 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT			0
6132 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK			0x000000f0
6138 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK			0x00000f00
6144 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK			0x0000f000
6150 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK			0x000f0000
6156 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK			0x00f00000
6162 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK			0x0f000000
6168 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK			0xf0000000
6175 #define REG_A6XX_SP_FS_OUTPUT_CNTL0				0x0000a98c
6176 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
6177 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK		0x0000ff00
6183 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK		0x00ff0000
6189 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK		0xff000000
6196 #define REG_A6XX_SP_FS_OUTPUT_CNTL1				0x0000a98d
6197 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
6198 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT			0
6204 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }  in REG_A6XX_SP_FS_MRT()
6206 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }  in REG_A6XX_SP_FS_MRT_REG()
6207 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK			0x000000ff
6208 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT			0
6213 #define A6XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
6214 #define A6XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200
6216 #define REG_A6XX_SP_FS_PREFETCH_CNTL				0x0000a99e
6217 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK			0x00000007
6218 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT			0
6223 #define A6XX_SP_FS_PREFETCH_CNTL_UNK3				0x00000008
6224 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK			0x00000ff0
6231 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }  in REG_A6XX_SP_FS_PREFETCH()
6233 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }  in REG_A6XX_SP_FS_PREFETCH_CMD()
6234 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK			0x0000007f
6235 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT			0
6240 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK			0x00000780
6246 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK			0x0000f800
6252 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK			0x003f0000
6258 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK			0x03c00000
6264 #define A6XX_SP_FS_PREFETCH_CMD_HALF				0x04000000
6265 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK			0xf8000000
6272 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }  in REG_A6XX_SP_FS_BINDLESS_PREFETCH()
6274 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*…  in REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD()
6275 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK		0x000000ff
6276 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT		0
6281 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK		0x00ff0000
6288 #define REG_A6XX_SP_FS_TEX_COUNT				0x0000a9a7
6290 #define REG_A6XX_SP_UNKNOWN_A9A8				0x0000a9a8
6292 #define REG_A6XX_SP_CS_UNKNOWN_A9B1				0x0000a9b1
6293 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK		0x00000001
6294 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT		0
6300 #define REG_A6XX_SP_CS_UNKNOWN_A9B3				0x0000a9b3
6302 #define REG_A6XX_SP_CS_TEX_COUNT				0x0000a9ba
6304 #define REG_A6XX_SP_FS_TEX_SAMP_LO				0x0000a9e0
6306 #define REG_A6XX_SP_FS_TEX_SAMP_HI				0x0000a9e1
6308 #define REG_A6XX_SP_CS_TEX_SAMP_LO				0x0000a9e2
6310 #define REG_A6XX_SP_CS_TEX_SAMP_HI				0x0000a9e3
6312 #define REG_A6XX_SP_FS_TEX_CONST_LO				0x0000a9e4
6314 #define REG_A6XX_SP_FS_TEX_CONST_HI				0x0000a9e5
6316 #define REG_A6XX_SP_CS_TEX_CONST_LO				0x0000a9e6
6318 #define REG_A6XX_SP_CS_TEX_CONST_HI				0x0000a9e7
6320 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }  in REG_A6XX_SP_CS_BINDLESS_BASE()
6322 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0;…  in REG_A6XX_SP_CS_BINDLESS_BASE_ADDR()
6324 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }  in REG_A6XX_SP_FS_OUTPUT()
6326 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }  in REG_A6XX_SP_FS_OUTPUT_REG()
6327 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK			0x000000ff
6328 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT			0
6333 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION			0x00000100
6335 #define REG_A6XX_SP_CS_CTRL_REG0				0x0000a9b0
6336 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
6342 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
6348 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
6354 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK			0x00100000
6360 #define A6XX_SP_CS_CTRL_REG0_VARYING				0x00400000
6361 #define A6XX_SP_CS_CTRL_REG0_DIFF_FINE				0x00800000
6362 #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE			0x04000000
6363 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS				0x80000000
6365 #define REG_A6XX_SP_CS_OBJ_START_LO				0x0000a9b4
6367 #define REG_A6XX_SP_CS_OBJ_START_HI				0x0000a9b5
6369 #define REG_A6XX_SP_CS_CONFIG					0x0000a9bb
6370 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX				0x00000001
6371 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP				0x00000002
6372 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO				0x00000004
6373 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO				0x00000008
6374 #define A6XX_SP_CS_CONFIG_ENABLED				0x00000100
6375 #define A6XX_SP_CS_CONFIG_NTEX__MASK				0x0001fe00
6381 #define A6XX_SP_CS_CONFIG_NSAMP__MASK				0x003e0000
6387 #define A6XX_SP_CS_CONFIG_NIBO__MASK				0x3fc00000
6394 #define REG_A6XX_SP_CS_INSTRLEN					0x0000a9bc
6396 #define REG_A6XX_SP_CS_IBO_LO					0x0000a9f2
6398 #define REG_A6XX_SP_CS_IBO_HI					0x0000a9f3
6400 #define REG_A6XX_SP_CS_IBO_COUNT				0x0000aa00
6402 #define REG_A6XX_SP_UNKNOWN_AB00				0x0000ab00
6404 #define REG_A6XX_SP_FS_CONFIG					0x0000ab04
6405 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX				0x00000001
6406 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP				0x00000002
6407 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO				0x00000004
6408 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO				0x00000008
6409 #define A6XX_SP_FS_CONFIG_ENABLED				0x00000100
6410 #define A6XX_SP_FS_CONFIG_NTEX__MASK				0x0001fe00
6416 #define A6XX_SP_FS_CONFIG_NSAMP__MASK				0x003e0000
6422 #define A6XX_SP_FS_CONFIG_NIBO__MASK				0x3fc00000
6429 #define REG_A6XX_SP_FS_INSTRLEN					0x0000ab05
6431 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }  in REG_A6XX_SP_BINDLESS_BASE()
6433 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }  in REG_A6XX_SP_BINDLESS_BASE_ADDR()
6435 #define REG_A6XX_SP_IBO_LO					0x0000ab1a
6437 #define REG_A6XX_SP_IBO_HI					0x0000ab1b
6439 #define REG_A6XX_SP_IBO_COUNT					0x0000ab20
6441 #define REG_A6XX_SP_2D_DST_FORMAT				0x0000acc0
6442 #define A6XX_SP_2D_DST_FORMAT_NORM				0x00000001
6443 #define A6XX_SP_2D_DST_FORMAT_SINT				0x00000002
6444 #define A6XX_SP_2D_DST_FORMAT_UINT				0x00000004
6445 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK		0x000007f8
6451 #define A6XX_SP_2D_DST_FORMAT_SRGB				0x00000800
6452 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK			0x0000f000
6459 #define REG_A6XX_SP_UNKNOWN_AE00				0x0000ae00
6461 #define REG_A6XX_SP_UNKNOWN_AE03				0x0000ae03
6463 #define REG_A6XX_SP_UNKNOWN_AE04				0x0000ae04
6465 #define REG_A6XX_SP_UNKNOWN_AE0F				0x0000ae0f
6467 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR		0x0000b180
6469 #define REG_A6XX_SP_UNKNOWN_B182				0x0000b182
6471 #define REG_A6XX_SP_UNKNOWN_B183				0x0000b183
6473 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL				0x0000b300
6474 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
6475 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
6481 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL				0x0000b301
6482 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
6483 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT		0
6488 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
6490 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR			0x0000b302
6492 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO		0x0000b302
6494 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI		0x0000b303
6496 #define REG_A6XX_SP_TP_SAMPLE_CONFIG				0x0000b304
6497 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0				0x00000001
6498 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE		0x00000002
6500 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0			0x0000b305
6501 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
6502 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
6507 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
6513 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
6519 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
6525 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
6531 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
6537 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
6543 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
6550 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1			0x0000b306
6551 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
6552 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
6557 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
6563 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
6569 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
6575 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
6581 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
6587 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
6593 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
6600 #define REG_A6XX_SP_TP_UNKNOWN_B309				0x0000b309
6602 #define REG_A6XX_SP_PS_2D_SRC_INFO				0x0000b4c0
6603 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK		0x000000ff
6604 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT		0
6609 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK			0x00000300
6615 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK			0x00000c00
6621 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS				0x00001000
6622 #define A6XX_SP_PS_2D_SRC_INFO_SRGB				0x00002000
6623 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK			0x0000c000
6629 #define A6XX_SP_PS_2D_SRC_INFO_FILTER				0x00010000
6630 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE			0x00040000
6631 #define A6XX_SP_PS_2D_SRC_INFO_UNK20				0x00100000
6632 #define A6XX_SP_PS_2D_SRC_INFO_UNK22				0x00400000
6634 #define REG_A6XX_SP_PS_2D_SRC_SIZE				0x0000b4c1
6635 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK			0x00007fff
6636 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT			0
6641 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK			0x3fff8000
6648 #define REG_A6XX_SP_PS_2D_SRC_LO				0x0000b4c2
6650 #define REG_A6XX_SP_PS_2D_SRC_HI				0x0000b4c3
6652 #define REG_A6XX_SP_PS_2D_SRC					0x0000b4c2
6654 #define REG_A6XX_SP_PS_2D_SRC_PITCH				0x0000b4c4
6655 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK			0x01fffe00
6662 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO				0x0000b4ca
6664 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI				0x0000b4cb
6666 #define REG_A6XX_SP_PS_2D_SRC_FLAGS				0x0000b4ca
6668 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH			0x0000b4cc
6669 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK		0x000007ff
6670 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT		0
6675 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK		0x003ff800
6682 #define REG_A6XX_SP_UNKNOWN_B600				0x0000b600
6684 #define REG_A6XX_SP_UNKNOWN_B605				0x0000b605
6686 #define REG_A6XX_HLSQ_VS_CNTL					0x0000b800
6687 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK			0x000000ff
6688 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT			0
6693 #define A6XX_HLSQ_VS_CNTL_ENABLED				0x00000100
6695 #define REG_A6XX_HLSQ_HS_CNTL					0x0000b801
6696 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK			0x000000ff
6697 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT			0
6702 #define A6XX_HLSQ_HS_CNTL_ENABLED				0x00000100
6704 #define REG_A6XX_HLSQ_DS_CNTL					0x0000b802
6705 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK			0x000000ff
6706 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT			0
6711 #define A6XX_HLSQ_DS_CNTL_ENABLED				0x00000100
6713 #define REG_A6XX_HLSQ_GS_CNTL					0x0000b803
6714 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK			0x000000ff
6715 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT			0
6720 #define A6XX_HLSQ_GS_CNTL_ENABLED				0x00000100
6722 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD			0x0000b820
6724 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR		0x0000b821
6726 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA			0x0000b823
6728 #define REG_A6XX_HLSQ_UNKNOWN_B980				0x0000b980
6730 #define REG_A6XX_HLSQ_CONTROL_1_REG				0x0000b982
6732 #define REG_A6XX_HLSQ_CONTROL_2_REG				0x0000b983
6733 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000000ff
6734 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT		0
6739 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK			0x0000ff00
6745 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK		0x00ff0000
6751 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK			0xff000000
6758 #define REG_A6XX_HLSQ_CONTROL_3_REG				0x0000b984
6759 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
6760 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
6765 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
6771 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
6777 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
6784 #define REG_A6XX_HLSQ_CONTROL_4_REG				0x0000b985
6785 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
6786 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
6791 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
6797 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
6803 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK		0xff000000
6810 #define REG_A6XX_HLSQ_CONTROL_5_REG				0x0000b986
6812 #define REG_A6XX_HLSQ_CS_CNTL					0x0000b987
6813 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK			0x000000ff
6814 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT			0
6819 #define A6XX_HLSQ_CS_CNTL_ENABLED				0x00000100
6821 #define REG_A6XX_HLSQ_CS_NDRANGE_0				0x0000b990
6822 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK			0x00000003
6823 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT			0
6828 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK			0x00000ffc
6834 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK			0x003ff000
6840 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK			0xffc00000
6847 #define REG_A6XX_HLSQ_CS_NDRANGE_1				0x0000b991
6848 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK		0xffffffff
6849 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT		0
6855 #define REG_A6XX_HLSQ_CS_NDRANGE_2				0x0000b992
6856 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK		0xffffffff
6857 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT		0
6863 #define REG_A6XX_HLSQ_CS_NDRANGE_3				0x0000b993
6864 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK		0xffffffff
6865 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT		0
6871 #define REG_A6XX_HLSQ_CS_NDRANGE_4				0x0000b994
6872 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK		0xffffffff
6873 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT		0
6879 #define REG_A6XX_HLSQ_CS_NDRANGE_5				0x0000b995
6880 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK		0xffffffff
6881 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT		0
6887 #define REG_A6XX_HLSQ_CS_NDRANGE_6				0x0000b996
6888 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK		0xffffffff
6889 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT		0
6895 #define REG_A6XX_HLSQ_CS_CNTL_0					0x0000b997
6896 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK			0x000000ff
6897 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT			0
6902 #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK				0x0000ff00
6908 #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK				0x00ff0000
6914 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK			0xff000000
6921 #define REG_A6XX_HLSQ_CS_UNKNOWN_B998				0x0000b998
6923 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X				0x0000b999
6925 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y				0x0000b99a
6927 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z				0x0000b99b
6929 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD			0x0000b9a0
6931 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR		0x0000b9a1
6933 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA			0x0000b9a3
6935 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }  in REG_A6XX_HLSQ_CS_BINDLESS_BASE()
6937 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i…  in REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR()
6939 #define REG_A6XX_HLSQ_DRAW_CMD					0x0000bb00
6940 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK			0x000000ff
6941 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT			0
6947 #define REG_A6XX_HLSQ_DISPATCH_CMD				0x0000bb01
6948 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
6949 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT			0
6955 #define REG_A6XX_HLSQ_EVENT_CMD					0x0000bb02
6956 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK			0x00ff0000
6962 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK				0x0000007f
6963 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT			0
6969 #define REG_A6XX_HLSQ_INVALIDATE_CMD				0x0000bb08
6970 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE			0x00000001
6971 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE			0x00000002
6972 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE			0x00000004
6973 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE			0x00000008
6974 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE			0x00000010
6975 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE			0x00000020
6976 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO				0x00000040
6977 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO			0x00000080
6978 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST		0x00080000
6979 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST		0x00000100
6980 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK		0x00003e00
6986 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK		0x0007c000
6993 #define REG_A6XX_HLSQ_FS_CNTL					0x0000bb10
6994 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK			0x000000ff
6995 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT			0
7000 #define A6XX_HLSQ_FS_CNTL_ENABLED				0x00000100
7002 #define REG_A6XX_HLSQ_SHARED_CONSTS				0x0000bb11
7003 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE				0x00000001
7005 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }  in REG_A6XX_HLSQ_BINDLESS_BASE()
7007 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }  in REG_A6XX_HLSQ_BINDLESS_BASE_ADDR()
7009 #define REG_A6XX_HLSQ_2D_EVENT_CMD				0x0000bd80
7010 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
7016 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK			0x0000007f
7017 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT			0
7023 #define REG_A6XX_HLSQ_UNKNOWN_BE00				0x0000be00
7025 #define REG_A6XX_HLSQ_UNKNOWN_BE01				0x0000be01
7027 #define REG_A6XX_HLSQ_UNKNOWN_BE04				0x0000be04
7029 #define REG_A6XX_CP_EVENT_START					0x0000d600
7030 #define A6XX_CP_EVENT_START_STATE_ID__MASK			0x000000ff
7031 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT			0
7037 #define REG_A6XX_CP_EVENT_END					0x0000d601
7038 #define A6XX_CP_EVENT_END_STATE_ID__MASK			0x000000ff
7039 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT			0
7045 #define REG_A6XX_CP_2D_EVENT_START				0x0000d700
7046 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK			0x000000ff
7047 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT			0
7053 #define REG_A6XX_CP_2D_EVENT_END				0x0000d701
7054 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK			0x000000ff
7055 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT			0
7061 #define REG_A6XX_TEX_SAMP_0					0x00000000
7062 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
7063 #define A6XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006
7069 #define A6XX_TEX_SAMP_0_XY_MIN__MASK				0x00000018
7075 #define A6XX_TEX_SAMP_0_WRAP_S__MASK				0x000000e0
7081 #define A6XX_TEX_SAMP_0_WRAP_T__MASK				0x00000700
7087 #define A6XX_TEX_SAMP_0_WRAP_R__MASK				0x00003800
7093 #define A6XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
7099 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK				0xfff80000
7106 #define REG_A6XX_TEX_SAMP_1					0x00000001
7107 #define A6XX_TEX_SAMP_1_UNK0					0x00000001
7108 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
7114 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF			0x00000010
7115 #define A6XX_TEX_SAMP_1_UNNORM_COORDS				0x00000020
7116 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR			0x00000040
7117 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
7123 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
7130 #define REG_A6XX_TEX_SAMP_2					0x00000002
7131 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK			0x00000003
7132 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT			0
7137 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR				0x00000020
7138 #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xffffff80
7145 #define REG_A6XX_TEX_SAMP_3					0x00000003
7147 #define REG_A6XX_TEX_CONST_0					0x00000000
7148 #define A6XX_TEX_CONST_0_TILE_MODE__MASK			0x00000003
7149 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT			0
7154 #define A6XX_TEX_CONST_0_SRGB					0x00000004
7155 #define A6XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
7161 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
7167 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
7173 #define A6XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
7179 #define A6XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
7185 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X			0x00010000
7186 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y			0x00040000
7187 #define A6XX_TEX_CONST_0_SAMPLES__MASK				0x00300000
7193 #define A6XX_TEX_CONST_0_FMT__MASK				0x3fc00000
7199 #define A6XX_TEX_CONST_0_SWAP__MASK				0xc0000000
7206 #define REG_A6XX_TEX_CONST_1					0x00000001
7207 #define A6XX_TEX_CONST_1_WIDTH__MASK				0x00007fff
7208 #define A6XX_TEX_CONST_1_WIDTH__SHIFT				0
7213 #define A6XX_TEX_CONST_1_HEIGHT__MASK				0x3fff8000
7220 #define REG_A6XX_TEX_CONST_2					0x00000002
7221 #define A6XX_TEX_CONST_2_UNK4					0x00000010
7222 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
7223 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
7228 #define A6XX_TEX_CONST_2_PITCH__MASK				0x1fffff80
7234 #define A6XX_TEX_CONST_2_TYPE__MASK				0x60000000
7240 #define A6XX_TEX_CONST_2_UNK31					0x80000000
7242 #define REG_A6XX_TEX_CONST_3					0x00000003
7243 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff
7244 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT			0
7249 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK			0x07800000
7255 #define A6XX_TEX_CONST_3_TILE_ALL				0x08000000
7256 #define A6XX_TEX_CONST_3_FLAG					0x10000000
7258 #define REG_A6XX_TEX_CONST_4					0x00000004
7259 #define A6XX_TEX_CONST_4_BASE_LO__MASK				0xffffffe0
7266 #define REG_A6XX_TEX_CONST_5					0x00000005
7267 #define A6XX_TEX_CONST_5_BASE_HI__MASK				0x0001ffff
7268 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT				0
7273 #define A6XX_TEX_CONST_5_DEPTH__MASK				0x3ffe0000
7280 #define REG_A6XX_TEX_CONST_6					0x00000006
7281 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK			0xffffff00
7288 #define REG_A6XX_TEX_CONST_7					0x00000007
7289 #define A6XX_TEX_CONST_7_FLAG_LO__MASK				0xffffffe0
7296 #define REG_A6XX_TEX_CONST_8					0x00000008
7297 #define A6XX_TEX_CONST_8_FLAG_HI__MASK				0x0001ffff
7298 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT				0
7304 #define REG_A6XX_TEX_CONST_9					0x00000009
7305 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK		0x0001ffff
7306 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
7312 #define REG_A6XX_TEX_CONST_10					0x0000000a
7313 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK		0x0000007f
7314 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT		0
7319 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK		0x00000f00
7325 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK		0x0000f000
7332 #define REG_A6XX_TEX_CONST_11					0x0000000b
7334 #define REG_A6XX_TEX_CONST_12					0x0000000c
7336 #define REG_A6XX_TEX_CONST_13					0x0000000d
7338 #define REG_A6XX_TEX_CONST_14					0x0000000e
7340 #define REG_A6XX_TEX_CONST_15					0x0000000f
7342 #define REG_A6XX_IBO_0						0x00000000
7343 #define A6XX_IBO_0_TILE_MODE__MASK				0x00000003
7344 #define A6XX_IBO_0_TILE_MODE__SHIFT				0
7349 #define A6XX_IBO_0_FMT__MASK					0x3fc00000
7356 #define REG_A6XX_IBO_1						0x00000001
7357 #define A6XX_IBO_1_WIDTH__MASK					0x00007fff
7358 #define A6XX_IBO_1_WIDTH__SHIFT					0
7363 #define A6XX_IBO_1_HEIGHT__MASK					0x3fff8000
7370 #define REG_A6XX_IBO_2						0x00000002
7371 #define A6XX_IBO_2_UNK4						0x00000010
7372 #define A6XX_IBO_2_PITCH__MASK					0x1fffff80
7378 #define A6XX_IBO_2_TYPE__MASK					0x60000000
7384 #define A6XX_IBO_2_UNK31					0x80000000
7386 #define REG_A6XX_IBO_3						0x00000003
7387 #define A6XX_IBO_3_ARRAY_PITCH__MASK				0x00003fff
7388 #define A6XX_IBO_3_ARRAY_PITCH__SHIFT				0
7393 #define A6XX_IBO_3_UNK27					0x08000000
7394 #define A6XX_IBO_3_FLAG						0x10000000
7396 #define REG_A6XX_IBO_4						0x00000004
7397 #define A6XX_IBO_4_BASE_LO__MASK				0xffffffff
7398 #define A6XX_IBO_4_BASE_LO__SHIFT				0
7404 #define REG_A6XX_IBO_5						0x00000005
7405 #define A6XX_IBO_5_BASE_HI__MASK				0x0001ffff
7406 #define A6XX_IBO_5_BASE_HI__SHIFT				0
7411 #define A6XX_IBO_5_DEPTH__MASK					0x3ffe0000
7418 #define REG_A6XX_IBO_6						0x00000006
7420 #define REG_A6XX_IBO_7						0x00000007
7422 #define REG_A6XX_IBO_8						0x00000008
7424 #define REG_A6XX_IBO_9						0x00000009
7425 #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK		0x0001ffff
7426 #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
7432 #define REG_A6XX_IBO_10						0x0000000a
7433 #define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK			0x0000007f
7434 #define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT			0
7440 #define REG_A6XX_UBO_0						0x00000000
7441 #define A6XX_UBO_0_BASE_LO__MASK				0xffffffff
7442 #define A6XX_UBO_0_BASE_LO__SHIFT				0
7448 #define REG_A6XX_UBO_1						0x00000001
7449 #define A6XX_UBO_1_BASE_HI__MASK				0x0001ffff
7450 #define A6XX_UBO_1_BASE_HI__SHIFT				0
7455 #define A6XX_UBO_1_SIZE__MASK					0xfffe0000
7462 #define REG_A6XX_PDC_GPU_ENABLE_PDC				0x00001140
7464 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR				0x00001148
7466 #define REG_A6XX_PDC_GPU_TCS0_CONTROL				0x00001540
7468 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK			0x00001541
7470 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK		0x00001542
7472 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID			0x00001543
7474 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR				0x00001544
7476 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA				0x00001545
7478 #define REG_A6XX_PDC_GPU_TCS1_CONTROL				0x00001572
7480 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK			0x00001573
7482 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK		0x00001574
7484 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID			0x00001575
7486 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR				0x00001576
7488 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA				0x00001577
7490 #define REG_A6XX_PDC_GPU_TCS2_CONTROL				0x000015a4
7492 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK			0x000015a5
7494 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK		0x000015a6
7496 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID			0x000015a7
7498 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR				0x000015a8
7500 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA				0x000015a9
7502 #define REG_A6XX_PDC_GPU_TCS3_CONTROL				0x000015d6
7504 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK			0x000015d7
7506 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK		0x000015d8
7508 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID			0x000015d9
7510 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR				0x000015da
7512 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA				0x000015db
7514 #define REG_A6XX_PDC_GPU_SEQ_MEM_0				0x00000000
7516 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A			0x00000000
7517 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK		0x000000ff
7518 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT		0
7523 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK	0x0000ff00
7530 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B			0x00000001
7532 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C			0x00000002
7534 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D			0x00000003
7536 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT			0x00000004
7537 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
7538 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
7543 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK		0x00007000
7549 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK		0xf0000000
7556 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM			0x00000005
7557 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK		0x0f000000
7564 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0			0x00000008
7566 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1			0x00000009
7568 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2			0x0000000a
7570 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3			0x0000000b
7572 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0			0x0000000c
7574 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1			0x0000000d
7576 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2			0x0000000e
7578 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3			0x0000000f
7580 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000010
7581 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
7582 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
7587 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
7593 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
7599 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
7605 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
7611 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
7617 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
7623 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
7630 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000011
7631 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
7632 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
7637 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
7643 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
7649 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
7655 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
7661 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
7667 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
7673 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
7680 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000002f
7682 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000030
7684 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0			0x00000001
7686 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1			0x00000002