33 	nvkm_mask(device, 0x61c128 + loff, 0x0000003f, watermark);  in g94_sor_dp_watermark()
42 	nvkm_mask(device, 0x61c10c + loff, 0x000001fc, TU << 2);  in g94_sor_dp_activesym()
43 	nvkm_mask(device, 0x61c128 + loff, 0x010f7f00, VTUa << 24 |  in g94_sor_dp_activesym()
53 	nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h);  in g94_sor_dp_audio_sym()
54 	nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v);  in g94_sor_dp_audio_sym()
65 	data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);  in g94_sor_dp_drive()
66 	data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);  in g94_sor_dp_drive()
67 	data[2] = nvkm_rd32(device, 0x61c130 + loff);  in g94_sor_dp_drive()
68 	if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0)  in g94_sor_dp_drive()
69 		data[2] = (data[2] & ~0x0000ff00) | (pu << 8);  in g94_sor_dp_drive()
70 	nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));  in g94_sor_dp_drive()
71 	nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));  in g94_sor_dp_drive()
72 	nvkm_wr32(device, 0x61c130 + loff, data[2]);  in g94_sor_dp_drive()
80 	nvkm_mask(device, 0x61c10c + loff, 0x0f000000, pattern << 24);  in g94_sor_dp_pattern()
89 	u32 mask = 0, i;  in g94_sor_dp_power()
91 	for (i = 0; i < nr; i++)  in g94_sor_dp_power()
94 	nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);  in g94_sor_dp_power()
95 	nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);  in g94_sor_dp_power()
97 		if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))  in g94_sor_dp_power()
108 	u32 dpctrl = 0x00000000;  in g94_sor_dp_links()
109 	u32 clksor = 0x00000000;  in g94_sor_dp_links()
113 		dpctrl |= 0x00004000;  in g94_sor_dp_links()
114 	if (sor->dp.bw > 0x06)  in g94_sor_dp_links()
115 		clksor |= 0x00040000;  in g94_sor_dp_links()
117 	nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor);  in g94_sor_dp_links()
118 	nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl);  in g94_sor_dp_links()
119 	return 0;  in g94_sor_dp_links()
128 		switch (nvkm_rd32(device, 0x614300 + soff) & 0x00030000) {  in g94_sor_war_needed()
129 		case 0x00000000:  in g94_sor_war_needed()
130 		case 0x00030000:  in g94_sor_war_needed()
151 		clksor = nvkm_rd32(device, 0x614300 + nv50_ior_base(ior));  in g94_sor_war_update_sppll1()
152 		switch (clksor & 0x03000000) {  in g94_sor_war_update_sppll1()
153 		case 0x02000000:  in g94_sor_war_update_sppll1()
154 		case 0x03000000:  in g94_sor_war_update_sppll1()
165 	nvkm_mask(device, 0x00e840, 0x80000000, 0x00000000);  in g94_sor_war_update_sppll1()
178 	sorpwr = nvkm_rd32(device, 0x61c004 + soff);  in g94_sor_war_3()
179 	if (sorpwr & 0x00000001) {  in g94_sor_war_3()
180 		u32 seqctl = nvkm_rd32(device, 0x61c030 + soff);  in g94_sor_war_3()
181 		u32  pd_pc = (seqctl & 0x00000f00) >> 8;  in g94_sor_war_3()
182 		u32  pu_pc =  seqctl & 0x0000000f;  in g94_sor_war_3()
184 		nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x1f008000);  in g94_sor_war_3()
187 			if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))  in g94_sor_war_3()
190 		nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000);  in g94_sor_war_3()
192 			if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))  in g94_sor_war_3()
196 		nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x00002000);  in g94_sor_war_3()
197 		nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f000000);  in g94_sor_war_3()
200 	nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000000);  in g94_sor_war_3()
201 	nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x00000000);  in g94_sor_war_3()
203 	if (sorpwr & 0x00000001) {  in g94_sor_war_3()
204 		nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000001);  in g94_sor_war_3()
219 	nvkm_mask(device, 0x00e840, 0x80000000, 0x80000000);  in g94_sor_war_2()
220 	nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x03000000);  in g94_sor_war_2()
221 	nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000001);  in g94_sor_war_2()
223 	nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x00000000);  in g94_sor_war_2()
224 	nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x14000000);  in g94_sor_war_2()
226 	nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x00000000);  in g94_sor_war_2()
227 	nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x01000000);  in g94_sor_war_2()
229 	if (nvkm_rd32(device, 0x61c004 + soff) & 0x00000001) {  in g94_sor_war_2()
230 		u32 seqctl = nvkm_rd32(device, 0x61c030 + soff);  in g94_sor_war_2()
231 		u32  pu_pc = seqctl & 0x0000000f;  in g94_sor_war_2()
232 		nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f008000);  in g94_sor_war_2()
241 	u32 ctrl = nvkm_rd32(device, 0x610794 + coff);  in g94_sor_state()
243 	state->proto_evo = (ctrl & 0x00000f00) >> 8;  in g94_sor_state()
245 	case 0: state->proto = LVDS; state->link = 1; break;  in g94_sor_state()
256 	state->head = ctrl & 0x00000003;  in g94_sor_state()
268 		.lanes = { 2, 1, 0, 3},
289 	*pmask = (nvkm_rd32(device, 0x610184) & 0x0f000000) >> 24;  in g94_sor_cnt()