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/qemu/pc-bios/dtb/
H A Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dbamboo.dts19 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clock-frequency = <0x1fca0550>;
35 timebase-frequency = <0x017d7840>;
36 i-cache-line-size = <0x20>;
37 d-cache-line-size = <0x20>;
38 i-cache-size = <0x8000>;
39 d-cache-size = <0x8000>;
[all …]
/qemu/target/microblaze/
H A Dcpu.h44 #define MB_CPU_IRQ 0
49 #define SR_PC 0
54 #define SR_BTR 0xb
55 #define SR_EDR 0xd
58 #define MSR_BE (1<<0) /* 0x001 */
59 #define MSR_IE (1<<1) /* 0x002 */
60 #define MSR_C (1<<2) /* 0x004 */
61 #define MSR_BIP (1<<3) /* 0x008 */
62 #define MSR_FSL (1<<4) /* 0x010 */
63 #define MSR_ICE (1<<5) /* 0x020 */
[all …]
/qemu/hw/display/
H A Dati_regs.h17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space
18 * 0x0100-0x0eff Misc regs only accessible via mmio
19 * 0x0f00-0x0fff Read-only copy of PCI config regs
20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
21 * 0x1400-0x1fff GUI (drawing engine) regs
29 #define MM_INDEX 0x0000
30 #define MM_DATA 0x0004
31 #define CLOCK_CNTL_INDEX 0x0008
32 #define CLOCK_CNTL_DATA 0x000c
33 #define BIOS_0_SCRATCH 0x0010
[all …]
/qemu/include/hw/m68k/
H A Dnext-cube.h28 #define DMA_ENABLE 0x01000000
29 #define DMA_SUPDATE 0x02000000
30 #define DMA_COMPLETE 0x08000000
32 #define DMA_M2DEV 0x0
33 #define DMA_SETENABLE 0x00010000
34 #define DMA_SETSUPDATE 0x00020000
35 #define DMA_DEV2M 0x00040000
36 #define DMA_CLRCOMPLETE 0x00080000
37 #define DMA_RESET 0x00100000
/qemu/hw/net/
H A Digb_regs.h14 #define E1000_DEV_ID_82576 0x10C9
15 #define E1000_DEV_ID_82576_FIBER 0x10E6
16 #define E1000_DEV_ID_82576_SERDES 0x10E7
17 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
18 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
19 #define E1000_DEV_ID_82576_NS 0x150A
20 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
21 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
45 #define E1000_ADVTXD_POTS_IXSM 0x00000100 /* Insert TCP/UDP Checksum */
46 #define E1000_ADVTXD_POTS_TXSM 0x00000200 /* Insert TCP/UDP Checksum */
[all …]
H A De1000x_regs.h36 #define E1000_DEV_ID_82542 0x1000
37 #define E1000_DEV_ID_82543GC_FIBER 0x1001
38 #define E1000_DEV_ID_82543GC_COPPER 0x1004
39 #define E1000_DEV_ID_82544EI_COPPER 0x1008
40 #define E1000_DEV_ID_82544EI_FIBER 0x1009
41 #define E1000_DEV_ID_82544GC_COPPER 0x100C
42 #define E1000_DEV_ID_82544GC_LOM 0x100D
43 #define E1000_DEV_ID_82540EM 0x100E
44 #define E1000_DEV_ID_82540EM_LOM 0x1015
45 #define E1000_DEV_ID_82540EP_LOM 0x1016
[all …]
/qemu/linux-user/include/host/ppc/
H A Dhost-signal.h35 return uc->uc_mcontext.regs->trap != 0x400 in host_signal_write()
36 && (uc->uc_mcontext.regs->dsisr & 0x02000000); in host_signal_write()
/qemu/linux-user/include/host/ppc64/
H A Dhost-signal.h37 return uc->uc_mcontext.gp_regs[PT_TRAP] != 0x400 in host_signal_write()
38 && (uc->uc_mcontext.gp_regs[PT_DSISR] & 0x02000000); in host_signal_write()
/qemu/target/ppc/
H A Duser_only_helper.c41 error_code = 0x40000000; in ppc_cpu_record_sigsegv()
44 error_code = 0x40000000; in ppc_cpu_record_sigsegv()
46 error_code |= 0x02000000; in ppc_cpu_record_sigsegv()
/qemu/include/hw/xen/interface/
H A Darch-arm.h153 #define XEN_HYPERCALL_TAG 0XEA1
182 _sxghr_tmp->q = 0; \
184 } while ( 0 )
277 #define _VGCF_online 0
293 #define XEN_DOMCTL_CONFIG_GIC_NATIVE 0
297 #define XEN_DOMCTL_CONFIG_TEE_NONE 0
316 * = 0 => property not present
317 * > 0 => Value of the property
345 #define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */
350 #define PSR_MODE_USR 0x10
[all …]
/qemu/qga/vss-win32/
H A Dvss-common.h56 const GUID g_gProviderId = { 0x3629d4ed, 0xee09, 0x4e0e,
57 {0x9a, 0x5c, 0x6d, 0x8b, 0xa2, 0x87, 0x2a, 0xef} };
58 const GUID g_gProviderVersion = { 0x11ef8b15, 0xcac6, 0x40d6,
59 {0x8d, 0x5c, 0x8f, 0xfc, 0x16, 0x3f, 0x24, 0xca} };
61 const CLSID CLSID_QGAVSSProvider = { 0x6e6a3492, 0x8d4d, 0x440c,
62 {0x96, 0x19, 0x5e, 0x5d, 0x0c, 0xc3, 0x1c, 0xa8} };
70 VSS_VOLSNAP_ATTR_NO_AUTORECOVERY = 0x00000002,
71 VSS_VOLSNAP_ATTR_TXF_RECOVERY = 0x02000000
/qemu/include/standard-headers/uefi/
H A Duefi.h49 #define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
51 #define EFI_HOB_TYPE_HANDOFF 0x0001
52 #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
53 #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
54 #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
55 #define EFI_HOB_TYPE_FV 0x0005
56 #define EFI_HOB_TYPE_CPU 0x0006
57 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
58 #define EFI_HOB_TYPE_FV2 0x0009
59 #define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A
[all …]
/qemu/include/hw/pci/
H A Dpcie_regs.h14 #define PCI_EXP_VER1_SIZEOF 0x14 /* express capability of ver. 1 */
15 #define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */
18 #define PCI_EXT_CAP_NEXT_MASK (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
80 #define PCI_EXP_DEVCAP2_EFF 0x100000
81 #define PCI_EXP_DEVCAP2_EETLPP 0x200000
83 #define PCI_EXP_DEVCTL2_EETLPPB 0x8000
99 #define PCI_ERR_SIZEOF 0x48
101 #define PCI_ERR_UNC_SDN 0x00000020 /* surprise down */
102 #define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
103 #define PCI_ERR_UNC_INTN 0x00400000 /* Internal Error */
[all …]
/qemu/include/hw/arm/
H A Dexynos4210.h38 #define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
39 #define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
40 #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */
42 #define EXYNOS4210_IROM_BASE_ADDR 0x00000000
43 #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */
44 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
45 #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */
47 #define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
48 #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */
52 #define EXYNOS4210_SMP_BOOT_SIZE 0x1000
[all …]
H A Dfsl-imx6.h86 #define FSL_IMX6_MMDC_ADDR 0x10000000
87 #define FSL_IMX6_MMDC_SIZE 0xF0000000
88 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
89 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
90 #define FSL_IMX6_IPU_2_ADDR 0x02800000
91 #define FSL_IMX6_IPU_2_SIZE 0x400000
92 #define FSL_IMX6_IPU_1_ADDR 0x02400000
93 #define FSL_IMX6_IPU_1_SIZE 0x400000
94 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
95 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/qemu/linux-headers/asm-generic/
H A Dmman-common.h10 #define PROT_READ 0x1 /* page can be read */
11 #define PROT_WRITE 0x2 /* page can be written */
12 #define PROT_EXEC 0x4 /* page can be executed */
13 #define PROT_SEM 0x8 /* page may be used for atomic ops */
14 /* 0x10 reserved for arch-specific use */
15 /* 0x20 reserved for arch-specific use */
16 #define PROT_NONE 0x0 /* page can not be accessed */
17 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
18 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
20 /* 0x01 - 0x03 are defined in linux/mman.h */
[all …]
/qemu/linux-headers/asm-mips/
H A Dmman.h18 #define PROT_NONE 0x00 /* page can not be accessed */
19 #define PROT_READ 0x01 /* page can be read */
20 #define PROT_WRITE 0x02 /* page can be written */
21 #define PROT_EXEC 0x04 /* page can be executed */
22 /* 0x08 reserved for PROT_EXEC_NOFLUSH */
23 #define PROT_SEM 0x10 /* page may be used for atomic ops */
24 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
25 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
30 /* 0x01 - 0x03 are defined in linux/mman.h */
31 #define MAP_TYPE 0x00f /* Mask for type of mapping */
[all …]
/qemu/hw/riscv/
H A Dshakti_c.c35 [SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
36 [SHAKTI_C_RAM] = { 0x80000000, 0x0 },
37 [SHAKTI_C_UART] = { 0x00011300, 0x00040 },
38 [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
39 [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
40 [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
41 [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
67 shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0); in shakti_c_machine_state_init()
112 (char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0, in type_init()
124 0, 1, false); in type_init()
[all …]
/qemu/include/
H A Delf.h22 #define PT_NULL 0
29 #define PT_LOOS 0x60000000
30 #define PT_HIOS 0x6fffffff
31 #define PT_LOPROC 0x70000000
32 #define PT_HIPROC 0x7fffffff
34 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
35 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
37 #define PT_MIPS_REGINFO 0x70000000
38 #define PT_MIPS_RTPROC 0x70000001
39 #define PT_MIPS_OPTIONS 0x70000002
[all …]
/qemu/include/system/
H A Ddevice_tree.h84 * array of strings to a sequential string with \0 separators before
129 for (unsigned i_ = 0; i_ < ARRAY_SIZE(qdt_tmp); i_++) { \
134 } while (0)
161 * Return value: 0 on success, <0 on error.
184 * Return value: 0 on success, <0 on error.
204 #define FDT_PCI_RANGE_RELOCATABLE 0x80000000
205 #define FDT_PCI_RANGE_PREFETCHABLE 0x40000000
206 #define FDT_PCI_RANGE_ALIASED 0x20000000
207 #define FDT_PCI_RANGE_TYPE_MASK 0x03000000
208 #define FDT_PCI_RANGE_MMIO_64BIT 0x03000000
[all …]
/qemu/include/hw/xen/
H A Dxen_native.h54 for (i = 0; i < size; i++) { in xendevicemodel_relocate_memory()
65 return 0; in xendevicemodel_relocate_memory()
77 #define XENMEM_resource_ioreq_server 0
79 #define XENMEM_resource_ioreq_server_frame_bufioreq 0
94 return 0; in xenforeignmemory_unmap_resource()
108 assert(addr == NULL && flags == 0); in xenforeignmemory_map2()
298 trace_xen_domid_restrict(rc ? errno : 0); in xen_restrict()
314 if (rc >= 0) { in xen_get_vmport_regs_pfn()
337 if (rc < 0) { in xen_get_default_ioreq_server_info()
345 if (rc < 0) { in xen_get_default_ioreq_server_info()
[all …]
/qemu/hw/ppc/
H A Dpnv_lpc.c37 ECCB_CTL = 0,
44 #define OPB_MASTER_LS_ROUTE0 0x8
45 #define OPB_MASTER_LS_ROUTE1 0xC
46 #define OPB_MASTER_LS_IRQ_STAT 0x50
47 #define OPB_MASTER_IRQ_LPC 0x00000800
48 #define OPB_MASTER_LS_IRQ_MASK 0x54
49 #define OPB_MASTER_LS_IRQ_POL 0x58
50 #define OPB_MASTER_LS_IRQ_INPUT 0x5c
53 #define LPC_HC_FW_SEG_IDSEL 0x24
54 #define LPC_HC_FW_RD_ACC_SIZE 0x28
[all …]
/qemu/hw/scsi/
H A Dmpi.h37 MPI_FUNCTION_SCSI_IO_REQUEST = 0x00,
38 MPI_FUNCTION_SCSI_TASK_MGMT = 0x01,
39 MPI_FUNCTION_IOC_INIT = 0x02,
40 MPI_FUNCTION_IOC_FACTS = 0x03,
41 MPI_FUNCTION_CONFIG = 0x04,
42 MPI_FUNCTION_PORT_FACTS = 0x05,
43 MPI_FUNCTION_PORT_ENABLE = 0x06,
44 MPI_FUNCTION_EVENT_NOTIFICATION = 0x07,
45 MPI_FUNCTION_EVENT_ACK = 0x08,
46 MPI_FUNCTION_FW_DOWNLOAD = 0x09,
[all …]
/qemu/target/hppa/
H A Dcpu.h48 #define PRIV_KERNEL 0
104 #define PSW_I 0x00000001
105 #define PSW_D 0x00000002
106 #define PSW_P 0x00000004
107 #define PSW_Q 0x00000008
108 #define PSW_R 0x00000010
109 #define PSW_F 0x00000020
110 #define PSW_G 0x00000040 /* PA1.x only */
111 #define PSW_O 0x00000080 /* PA2.0 only */
112 #define PSW_CB 0x0000ff00
[all …]

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