Lines Matching +full:0 +full:x02000000

14 #define PCI_EXP_VER1_SIZEOF             0x14 /* express capability of ver. 1 */
15 #define PCI_EXP_VER2_SIZEOF             0x3c /* express capability of ver. 2 */
18 #define PCI_EXT_CAP_NEXT_MASK           (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
80 #define PCI_EXP_DEVCAP2_EFF             0x100000
81 #define PCI_EXP_DEVCAP2_EETLPP          0x200000
83 #define PCI_EXP_DEVCTL2_EETLPPB         0x8000
99 #define PCI_ERR_SIZEOF                  0x48
101 #define PCI_ERR_UNC_SDN                 0x00000020      /* surprise down */
102 #define PCI_ERR_UNC_ACSV                0x00200000      /* ACS Violation */
103 #define PCI_ERR_UNC_INTN                0x00400000      /* Internal Error */
104 #define PCI_ERR_UNC_MCBTLP              0x00800000      /* MC Blcoked TLP */
105 #define PCI_ERR_UNC_ATOP_EBLOCKED       0x01000000      /* atomic op egress blocked */
106 #define PCI_ERR_UNC_TLP_PRF_BLOCKED     0x02000000      /* TLP Prefix Blocked */
107 #define PCI_ERR_COR_ADV_NONFATAL        0x00002000      /* Advisory Non-Fatal */
108 #define PCI_ERR_COR_INTERNAL            0x00004000      /* Corrected Internal */
109 #define PCI_ERR_COR_HL_OVERFLOW         0x00008000      /* Header Long Overflow */
110 #define PCI_ERR_CAP_FEP_MASK            0x0000001f
111 #define PCI_ERR_CAP_MHRC                0x00000200
112 #define PCI_ERR_CAP_MHRE                0x00000400
113 #define PCI_ERR_CAP_TLP                 0x00000800
116 #define PCI_ERR_TLP_PREFIX_LOG          0x38
119 #define PCI_SEC_STATUS_RCV_SYSTEM_ERROR         0x4000
127 #define PCI_ERR_ROOT_IRQ                0xf8000000
178 #define PCI_ACS_VER                     0x1
182 #define PCI_DOE_VER                     0x1