Lines Matching +full:0 +full:x02000000
37 ECCB_CTL = 0,
44 #define OPB_MASTER_LS_ROUTE0 0x8
45 #define OPB_MASTER_LS_ROUTE1 0xC
46 #define OPB_MASTER_LS_IRQ_STAT 0x50
47 #define OPB_MASTER_IRQ_LPC 0x00000800
48 #define OPB_MASTER_LS_IRQ_MASK 0x54
49 #define OPB_MASTER_LS_IRQ_POL 0x58
50 #define OPB_MASTER_LS_IRQ_INPUT 0x5c
53 #define LPC_HC_FW_SEG_IDSEL 0x24
54 #define LPC_HC_FW_RD_ACC_SIZE 0x28
55 #define LPC_HC_FW_RD_1B 0x00000000
56 #define LPC_HC_FW_RD_2B 0x01000000
57 #define LPC_HC_FW_RD_4B 0x02000000
58 #define LPC_HC_FW_RD_16B 0x04000000
59 #define LPC_HC_FW_RD_128B 0x07000000
60 #define LPC_HC_IRQSER_CTRL 0x30
61 #define LPC_HC_IRQSER_EN 0x80000000
62 #define LPC_HC_IRQSER_QMODE 0x40000000
63 #define LPC_HC_IRQSER_START_MASK 0x03000000
64 #define LPC_HC_IRQSER_START_4CLK 0x00000000
65 #define LPC_HC_IRQSER_START_6CLK 0x01000000
66 #define LPC_HC_IRQSER_START_8CLK 0x02000000
67 #define LPC_HC_IRQSER_AUTO_CLEAR 0x00800000
68 #define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */
69 #define LPC_HC_IRQSTAT 0x38
70 #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
71 #define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
72 #define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000
73 #define LPC_HC_IRQ_LRESET 0x00000400
74 #define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080
75 #define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040
76 #define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020
77 #define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010
78 #define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008
79 #define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004
80 #define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002
81 #define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001
82 #define LPC_HC_ERROR_ADDRESS 0x40
84 #define LPC_OPB_SIZE 0x100000000ull
86 #define ISA_IO_SIZE 0x00010000
87 #define ISA_MEM_SIZE 0x10000000
88 #define ISA_FW_SIZE 0x100000000
89 #define LPC_IO_OPB_ADDR 0xd0010000
90 #define LPC_IO_OPB_SIZE 0x00010000
91 #define LPC_MEM_OPB_ADDR 0xe0000000
92 #define LPC_MEM_OPB_SIZE 0x10000000
93 #define LPC_FW_OPB_ADDR 0xf0000000
94 #define LPC_FW_OPB_SIZE 0x10000000
96 #define LPC_OPB_REGS_OPB_ADDR 0xc0010000
97 #define LPC_OPB_REGS_OPB_SIZE 0x00000060
98 #define LPC_OPB_REGS_OPBA_ADDR 0xc0011000
99 #define LPC_OPB_REGS_OPBA_SIZE 0x00000008
100 #define LPC_HC_REGS_OPB_ADDR 0xc0012000
101 #define LPC_HC_REGS_OPB_SIZE 0x00000100
105 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; in pnv_lpc_dt_xscom()
123 return 0; in pnv_lpc_dt_xscom()
130 const char compat[] = "ibm,power9-lpcm-opb\0simple-bus"; in pnv_dt_lpc()
131 const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc"; in pnv_dt_lpc()
134 uint32_t opb_ranges[8] = { 0, in pnv_dt_lpc()
148 uint32_t lpc_ranges[12] = { 0, 0, in pnv_dt_lpc()
151 cpu_to_be32(1), 0, in pnv_dt_lpc()
154 cpu_to_be32(3), 0, in pnv_dt_lpc()
184 reg[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR); in pnv_dt_lpc()
198 reg[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR); in pnv_dt_lpc()
212 reg[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR); in pnv_dt_lpc()
218 name = g_strdup_printf("lpc@0"); in pnv_dt_lpc()
229 return 0; in pnv_dt_lpc()
263 #define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH)
275 "ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz); in pnv_lpc_do_eccb()
283 (((uint64_t)data[0]) << 24 | in pnv_lpc_do_eccb()
289 (0xffffffffull << ECCB_STAT_RD_DATA_LSH); in pnv_lpc_do_eccb()
292 data[0] = lpc->eccb_data_reg >> 24; in pnv_lpc_do_eccb()
307 uint64_t val = 0; in pnv_lpc_xscom_read()
312 val = 0; in pnv_lpc_xscom_read()
316 lpc->eccb_stat_reg = 0; in pnv_lpc_xscom_read()
361 uint64_t val = 0; in pnv_lpc_mmio_read()
375 qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%" in pnv_lpc_mmio_read()
377 return 0; in pnv_lpc_mmio_read()
382 qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%" in pnv_lpc_mmio_read()
406 qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%" in pnv_lpc_mmio_write()
413 qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%" in pnv_lpc_mmio_write()
446 for (irq = 0; irq <= 13; irq++) { in pnv_lpc_eval_serirq_routes()
461 uint32_t active_irqs = 0; in pnv_lpc_eval_irqs()
479 for (irq = 0; irq < ISA_NUM_IRQS; irq++) { in pnv_lpc_eval_irqs()
485 qemu_set_irq(lpc->psi_irq_serirq[0], serirq_out[0]); in pnv_lpc_eval_irqs()
515 qemu_set_irq(lpc->psi_irq_lpchc, lpc->opb_irq_stat != 0); in pnv_lpc_eval_irqs()
527 uint64_t val = 0xfffffffffffffffful; in lpc_hc_read()
549 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%" in lpc_hc_read()
568 val &= 0xf; /* Selects device 0-15 */ in lpc_hc_write()
597 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%" in lpc_hc_write()
619 uint64_t val = 0xfffffffffffffffful; in opb_master_read()
641 qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%" in opb_master_read()
680 qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%" in opb_master_write()
681 HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val); in opb_master_write()
801 memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull); in pnv_lpc_realize()
814 &lpc->isa_io, 0, LPC_IO_OPB_SIZE); in pnv_lpc_realize()
818 &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE); in pnv_lpc_realize()
822 &lpc->isa_fw, 0, LPC_FW_OPB_SIZE); in pnv_lpc_realize()
896 qemu_set_irq(lpc->psi_irq_lpchc, pnv->cpld_irqstate != 0); in type_init()