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/linux-5.10/arch/arm/include/asm/hardware/
Dentry-macro-iomd.S2 * arch/arm/include/asm/hardware/entry-macro-iomd.S
4 * Low-level IRQ helper macros for IOC/IOMD based platforms
17 teq \irqstat, #0
21 teqeq \irqstat, #0
26 teqeq \irqstat, #0
30 teqeq \irqstat, #0
35 teqeq \irqstat, #0
45 irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
62 irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
79 irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl502d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
[all …]
Dcl902d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
[all …]
Dcl5039.h2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
[all …]
Dcl507c.h2 * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
27 #define NV_DISP_BASE_NOTIFIER_1 0x00000000
28 #define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004
29 #define NV_DISP_BASE_NOTIFIER_1__0 0x00000000
30 #define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0
32 #define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30
33 #define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000
34 #define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001
35 #define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002
39 #define NV507C_DMA 0x00000000
[all …]
/linux-5.10/arch/powerpc/lib/
Dfeature-fixups-test.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <asm/feature-fixups.h>
9 #include <asm/asm-compat.h>
10 #include <asm/ppc-opcode.h>
48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
[all …]
/linux-5.10/arch/powerpc/xmon/
Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
135 #define UNUSED 0
136 { 0, 0, NULL, NULL, 0 },
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
152 #define BB_MASK (0x1f << 11)
[all …]
/linux-5.10/drivers/infiniband/hw/i40iw/
Di40iw_register.h3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
38 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
40 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
41 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
42 #define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
44 #define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
45 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31
46 #define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
[all …]
/linux-5.10/Documentation/userspace-api/media/v4l/
Dpixfmt-meta-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
Dpixfmt-meta-vsp1-hgt.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
51 <0..............................Hue Value............................255>
[all …]
/linux-5.10/drivers/video/fbdev/nvidia/
Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/linux-5.10/drivers/infiniband/hw/hns/
Dhns_roce_hw_v2.h2 * Copyright (c) 2016-2017 Hisilicon Limited.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
48 #define HNS_ROCE_V2_MAX_QP_NUM 0x100000
49 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
50 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
51 #define HNS_ROCE_V2_MAX_SRQ 0x100000
52 #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
54 #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
55 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100
[all …]
/linux-5.10/arch/mips/include/asm/octeon/
Dcvmx-ciu2-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 …ine CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * …
32 …ine CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * …
33 … CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * …
34 …CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * …
35 …CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * …
36 …_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * …
37 …_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * …
[all …]
Dcvmx-pexp-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31…
32 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
33 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
34 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
35 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
36 #define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
37 #define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
[all …]
/linux-5.10/drivers/net/dsa/sja1105/
Dsja1105_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 #define SJA1105_SIZE_MAC_AREA (0x02 * 4)
7 #define SJA1105_SIZE_HL1_AREA (0x10 * 4)
8 #define SJA1105_SIZE_HL2_AREA (0x4 * 4)
9 #define SJA1105_SIZE_QLEVEL_AREA (0x8 * 4) /* 0x4 to 0xB */
10 #define SJA1105_SIZE_ETHER_AREA (0x17 * 4)
107 sja1105_unpack(p + 0x0, &status->n_runt, 31, 24, 4); in sja1105_port_status_mac_unpack()
108 sja1105_unpack(p + 0x0, &status->n_soferr, 23, 16, 4); in sja1105_port_status_mac_unpack()
109 sja1105_unpack(p + 0x0, &status->n_alignerr, 15, 8, 4); in sja1105_port_status_mac_unpack()
[all …]
/linux-5.10/arch/alpha/include/asm/
Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
32 .prologue 0 \n\
36 ldq $0,0($17) \n\
37 ldq $1,0($18) \n\
54 xor $0,$1,$0 # 7 cycles from $1 load \n\
58 stq $0,0($17) \n\
87 .prologue 0 \n\
91 ldq $0,0($17) \n\
[all …]
/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h1 /* SPDX-License-Identifier: ISC */
6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
18 PKT_TYPE_TXS = 0,
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
[all …]
Dregs.h1 /* SPDX-License-Identifier: ISC */
6 #define MT_HW_REV 0x1000
7 #define MT_HW_CHIPID 0x1008
8 #define MT_TOP_MISC2 0x1134
10 #define MT_MCU_BASE 0x2000
13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
[all …]
/linux-5.10/arch/m68k/include/asm/
Dbitops.h22 * ColdFire - supports standard bset/bclr/bchg with register operand only
23 * 68000 - supports standard bset/bclr/bchg with memory operand
24 * >= 68020 - also supports the bfset/bfclr/bfchg instructions
33 char *p = (char *)vaddr + (nr ^ 31) / 8; in bset_reg_set_bit()
35 __asm__ __volatile__ ("bset %1,(%0)" in bset_reg_set_bit()
43 char *p = (char *)vaddr + (nr ^ 31) / 8; in bset_mem_set_bit()
45 __asm__ __volatile__ ("bset %1,%0" in bset_mem_set_bit()
52 __asm__ __volatile__ ("bfset %1{%0:#1}" in bfset_mem_set_bit()
54 : "d" (nr ^ 31), "o" (*vaddr) in bfset_mem_set_bit()
73 char *p = (char *)vaddr + (nr ^ 31) / 8; in bclr_reg_clear_bit()
[all …]
/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
34 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
48 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
50 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
68 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
70 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
79 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
81 #define MT_RXV1_ACID_DET_H BIT(31)
[all …]
/linux-5.10/arch/alpha/lib/
Dclear_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
13 .prologue 0
15 lda $0,128
20 1: stq $31,0($16)
21 stq $31,8($16)
22 stq $31,16($16)
23 stq $31,24($16)
25 stq $31,32($16)
26 stq $31,40($16)
27 stq $31,48($16)
[all …]
Dev6-clear_page.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-clear_page.S
13 .prologue 0
15 lda $0,128
26 stq $31,0($16)
27 subq $0,1,$0
30 stq $31,8($16)
31 stq $31,16($16)
35 stq $31,24($16)
36 stq $31,32($16)
[all …]
/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR 0x000054C8
13 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK 0x00001000
14 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSKN 0xFFFFEFFF
17 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_DEFAULT 0x0
21 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR 0x000054C8
22 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK 0x000001FF
23 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSKN 0xFFFFFE00
24 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT 0
33 #define HW_ATL2_RPF_NEW_EN_ADR 0x00005104
[all …]
/linux-5.10/arch/parisc/math-emu/
Dfloat.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
26 PA header file -- do not include this header file for non-PA builds.
41 * floating-point precisions.
44 * +-------+-------+-------+-------+-------+-------+-------+-------+
46 * +-------+-------+-------+-------+-------+-------+-------+-------+
49 #define Ssign(object) Bitfield_extract( 0, 1,object)
50 #define Ssignedsign(object) Bitfield_signed_extract( 0, 1,object)
[all …]
/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
32 "osc24M", 0x000,
35 0, 2, /* M */
36 BIT(31), /* gate */
[all …]

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