Lines Matching +full:0 +full:- +full:31
2 * Copyright (c) 2016-2017 Hisilicon Limited.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
48 #define HNS_ROCE_V2_MAX_QP_NUM 0x100000
49 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
50 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
51 #define HNS_ROCE_V2_MAX_SRQ 0x100000
52 #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
54 #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
55 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100
56 #define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
57 #define HNS_ROCE_V2_MAX_CQE_NUM 0x400000
58 #define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000
61 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
62 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
70 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000
71 #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
72 #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
73 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
74 #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
75 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
95 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
97 #define HNS_ROCE_INVALID_LKEY 0x100
125 #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
144 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
147 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
154 NO_ARMED = 0x0,
155 REG_NXT_CEQE = 0x2,
156 REG_NXT_SE_CEQE = 0x3
159 #define V2_CQ_DB_REQ_NOT_SOL 0
163 #define V2_QKEY_VAL 0x80010000
167 #define HNS_ROCE_V2_CQE_QPN_MASK 0xfffff
170 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
171 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
172 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
173 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
174 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
175 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
176 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
177 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
178 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
179 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
180 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
181 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
182 HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc,
183 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
188 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
189 HNS_ROCE_V2_OPCODE_SEND = 0x1,
190 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
191 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
195 HNS_ROCE_V2_SQ_DB = 0x0,
196 HNS_ROCE_V2_RQ_DB = 0x1,
197 HNS_ROCE_V2_SRQ_DB = 0x2,
198 HNS_ROCE_V2_CQ_DB_PTR = 0x3,
199 HNS_ROCE_V2_CQ_DB_NTR = 0x4,
203 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
204 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
205 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
206 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
207 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
208 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
209 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
210 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
211 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
212 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
213 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
214 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
215 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
216 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
217 HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23,
219 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
224 HNS_QUERY_FW_VER = 0x0001,
225 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
226 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
227 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
228 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
229 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
230 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
231 HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404,
232 HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406,
233 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408,
234 HNS_ROCE_OPC_CFG_ENTRY_SIZE = 0x8409,
235 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
236 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
237 HNS_ROCE_OPC_POST_MB = 0x8504,
238 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
239 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
240 HNS_ROCE_OPC_FUNC_CLEAR = 0x8508,
241 HNS_ROCE_OPC_CLR_SCCC = 0x8509,
242 HNS_ROCE_OPC_QUERY_SCCC = 0x850a,
243 HNS_ROCE_OPC_RESET_SCCC = 0x850b,
244 HNS_SWITCH_PARAMETER_CFG = 0x1033,
253 CMD_EXEC_SUCCESS = 0,
260 GID_TYPE_FLAG_ROCE_V1 = 0,
283 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
284 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
286 #define V2_CQC_BYTE_4_CQ_ST_S 0
287 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
310 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
312 #define V2_CQC_BYTE_8_CQN_S 0
313 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
318 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
319 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
322 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
324 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
325 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
331 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
333 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
334 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
336 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
337 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
339 #define V2_CQC_BYTE_40_CQE_BA_S 0
340 #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
342 #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0
345 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
347 #define V2_CQC_BYTE_52_CQE_CNT_S 0
348 #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
350 #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
351 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
354 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
356 #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
357 #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
378 #define SRQC_BYTE_4_SRQ_ST_S 0
379 #define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0)
388 #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
390 #define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0
391 #define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0)
393 #define SRQC_BYTE_12_SRQ_XRCD_S 0
394 #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
396 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0
397 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0)
399 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0
400 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
402 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0
403 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0)
405 #define SRQC_BYTE_28_PD_S 0
406 #define SRQC_BYTE_28_PD_M GENMASK(23, 0)
411 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0
412 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0)
414 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0
415 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0)
424 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
426 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0
427 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0)
429 #define SRQC_BYTE_56_SRQ_XRC_CQN_S 0
430 #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
436 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
438 #define SRQC_BYTE_60_SRQ_RECORD_EN_S 0
441 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
444 V2_MPT_ST_VALID = 0x1,
445 V2_MPT_ST_FREE = 0x2,
524 #define V2_QPC_BYTE_4_TST_S 0
525 #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
531 #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
533 #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
534 #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
539 #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
541 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
542 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
548 #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
550 #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
551 #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
569 #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
571 #define V2_QPC_BYTE_24_HOP_LIMIT_S 0
572 #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
581 #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
583 #define V2_QPC_BYTE_28_FL_S 0
584 #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
596 #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
598 #define V2_QPC_BYTE_52_DMAC_S 0
599 #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
602 #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
604 #define V2_QPC_BYTE_56_DQPN_S 0
605 #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
613 #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
615 #define V2_QPC_BYTE_60_TEMPID_S 0
616 #define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
626 #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
628 #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
631 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
633 #define V2_QPC_BYTE_76_SRQN_S 0
634 #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
647 #define V2_QPC_BYTE_80_RX_CQN_S 0
648 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
651 #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
653 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
654 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
657 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
659 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
660 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
663 #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
665 #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
666 #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
668 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
669 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
672 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
674 #define V2_QPC_BYTE_108_INV_CREDIT_S 0
684 #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
686 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
687 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
693 #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
695 #define V2_QPC_BYTE_140_TRRL_BA_S 0
696 #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
707 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
709 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
710 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
715 #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
717 #define V2_QPC_BYTE_148_RQ_MSN_S 0
718 #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
721 #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
723 #define V2_QPC_BYTE_152_RAQ_PSN_S 0
724 #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
727 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
729 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
730 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
732 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
733 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
736 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
738 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
739 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
753 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
755 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
756 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
763 #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
765 #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
766 #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
769 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
771 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
772 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
775 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
777 #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
778 #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
781 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
783 #define V2_QPC_BYTE_196_IRRL_HEAD_S 0
784 #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
787 #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
789 #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
790 #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
793 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
795 #define V2_QPC_BYTE_208_IRRL_BA_S 0
796 #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
805 #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
807 #define V2_QPC_BYTE_212_LSN_S 0
808 #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
817 #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
819 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
820 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
823 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
825 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
826 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
829 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
831 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
832 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
839 #define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
841 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
842 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
848 #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
850 #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
851 #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
860 #define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
862 #define V2_QPC_BYTE_248_IRRL_PSN_S 0
863 #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
874 #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
876 #define V2_QPC_BYTE_252_TX_CQN_S 0
877 #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
882 #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
884 #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
885 #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
888 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
909 #define V2_CQE_BYTE_4_OPCODE_S 0
910 #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
922 #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
924 #define V2_CQE_BYTE_12_XRC_SRQN_S 0
925 #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
927 #define V2_CQE_BYTE_16_LCL_QPN_S 0
928 #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
931 #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
933 #define V2_CQE_BYTE_28_SMAC_4_S 0
934 #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0)
947 #define V2_CQE_BYTE_32_RMT_QPN_S 0
948 #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
958 #define V2_CQE_BYTE_32_LPK_S 31
979 #define V2_MPT_BYTE_4_MPT_ST_S 0
980 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
989 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
991 #define V2_MPT_BYTE_8_RA_EN_S 0
1008 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
1010 #define V2_MPT_BYTE_12_FRE_S 0
1023 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
1025 #define V2_MPT_BYTE_48_PBL_BA_H_S 0
1026 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
1030 #define V2_MPT_BYTE_56_PA0_H_S 0
1031 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
1033 #define V2_MPT_BYTE_64_PA1_H_S 0
1034 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
1037 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
1039 #define V2_DB_BYTE_4_TAG_S 0
1040 #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
1045 #define V2_DB_PARAMETER_IDX_S 0
1046 #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0)
1051 #define V2_CQ_DB_BYTE_4_TAG_S 0
1052 #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
1057 #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0
1058 #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
1081 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
1082 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1090 #define V2_UD_SEND_WQE_BYTE_16_PD_S 0
1091 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
1094 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1096 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1097 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1100 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
1102 #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
1103 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
1105 #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
1106 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
1112 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
1114 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
1115 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
1125 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
1127 #define V2_UD_SEND_WQE_DMAC_0_S 0
1128 #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0)
1137 #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
1139 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0
1140 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0)
1149 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
1164 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
1165 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1189 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1190 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1193 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1195 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1196 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1198 #define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31
1238 #define FUNC_CLEAR_RST_FUN_DONE_S 0
1256 #define CFG_LLM_QUE_DEPTH_S 0
1257 #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
1265 #define CFG_LLM_HEAD_PTR_S 0
1266 #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
1275 #define CFG_LLM_TAIL_BA_H_S 0
1276 #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
1278 #define CFG_LLM_TAIL_PTR_S 0
1279 #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
1286 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
1287 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
1290 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
1301 #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
1302 #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
1307 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
1308 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
1313 #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
1314 #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
1319 #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
1320 #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
1325 #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
1326 #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
1340 #define PF_RES_DATA_1_PF_SMAC_IDX_S 0
1341 #define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0)
1346 #define PF_RES_DATA_2_PF_SGID_IDX_S 0
1347 #define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0)
1352 #define PF_RES_DATA_3_PF_QID_IDX_S 0
1353 #define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0)
1358 #define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0
1359 #define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0)
1371 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0
1372 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0)
1377 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0
1378 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0)
1392 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
1393 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
1398 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
1399 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
1404 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
1405 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
1410 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
1411 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
1416 #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
1417 #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
1431 #define VF_RES_B_DATA_0_VF_ID_S 0
1432 #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
1434 #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
1435 #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
1440 #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
1441 #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
1446 #define VF_RES_B_DATA_3_VF_QID_IDX_S 0
1447 #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
1452 #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0
1453 #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0)
1497 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
1498 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
1506 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0
1507 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
1515 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0
1516 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
1524 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0
1525 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
1533 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0
1534 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0)
1552 HNS_ROCE_CFG_QPC_SIZE = BIT(0),
1562 #define CFG_SGID_TB_TABLE_IDX_S 0
1563 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1565 #define CFG_SGID_TB_VF_SGID_TYPE_S 0
1566 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1574 #define CFG_SMAC_TB_IDX_S 0
1575 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1577 #define CFG_SMAC_TB_VF_SMAC_H_S 0
1578 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1630 #define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0
1631 #define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0)
1634 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20)
1636 #define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0
1637 #define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0)
1642 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0
1643 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0)
1645 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0
1646 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0)
1648 #define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0
1649 #define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0)
1663 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0
1664 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0)
1676 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0
1677 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0)
1680 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22)
1682 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0
1683 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0)
1691 #define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0
1692 #define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0)
1697 #define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0
1698 #define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0)
1714 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0
1715 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0)
1718 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20)
1720 #define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0
1721 #define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0)
1723 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0
1724 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0)
1726 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0
1727 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0)
1739 #define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1740 #define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
1779 #define HNS_ROCE_LINK_TABLE_BA1_S 0
1780 #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
1783 #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1807 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1808 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1809 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1810 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1812 #define HNS_ROCE_V2_EQ_STATE_INVALID 0
1817 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1820 #define HNS_ROCE_V2_EQ_COALESCE_0 0
1823 #define HNS_ROCE_V2_EQ_FIRED 0
1827 #define HNS_ROCE_EQ_INIT_EQE_CNT 0
1828 #define HNS_ROCE_EQ_INIT_PROD_IDX 0
1829 #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1830 #define HNS_ROCE_EQ_INIT_MSI_IDX 0
1831 #define HNS_ROCE_EQ_INIT_CONS_IDX 0
1832 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1834 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1835 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1837 #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1838 #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1840 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1844 #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1845 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1846 #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1847 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1850 #define EQ_DISABLE 0
1852 #define EQ_REG_OFFSET 0x4
1855 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1857 #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
1859 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1860 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1861 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1862 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1863 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1866 #define HNS_ROCE_EQC_EQ_ST_S 0
1867 #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
1885 #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
1888 #define HNS_ROCE_EQC_BA_PG_SZ_S 0
1889 #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
1895 #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
1898 #define HNS_ROCE_EQC_MAX_CNT_S 0
1899 #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
1902 #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
1905 #define HNS_ROCE_EQC_REPORT_TIMER_S 0
1906 #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
1909 #define HNS_ROCE_EQC_EQE_BA_L_S 0
1910 #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
1913 #define HNS_ROCE_EQC_EQE_BA_H_S 0
1914 #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
1917 #define HNS_ROCE_EQC_SHIFT_S 0
1918 #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
1924 #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
1927 #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
1928 #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
1931 #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
1932 #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
1935 #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
1938 #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
1939 #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
1942 #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
1943 #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
1948 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1949 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1951 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1952 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1960 #define HNS_ROCE_V2_EQ_DB_TAG_S 0
1961 #define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0)
1963 #define HNS_ROCE_V2_EQ_DB_PARA_S 0
1964 #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
1966 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1967 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1969 #define MAX_SERVICE_LEVEL 0x7
1992 struct hns_roce_v2_priv *priv = hr_dev->priv; in hns_roce_write64()
1993 struct hnae3_handle *handle = priv->handle; in hns_roce_write64()
1994 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; in hns_roce_write64()
1996 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) in hns_roce_write64()