mt76/mt7615/mac.h

1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_LENGTH			GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE		GENMASK(31, 29)
34 #define MT_RXD1_NORMAL_BSSID		GENMASK(31, 26)
48 #define MT_RXD1_NORMAL_HTC_VLD		BIT(0)
50 #define MT_RXD2_NORMAL_NON_AMPDU	BIT(31)
68 #define MT_RXD2_NORMAL_WLAN_IDX		GENMASK(7, 0)
70 #define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
79 #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
81 #define MT_RXV1_ACID_DET_H		BIT(31)
95 #define MT_RXV1_TX_RATE			GENMASK(6, 0)
97 #define MT_RXV2_SEL_ANT			BIT(31)
101 #define MT_RXV2_LENGTH			GENMASK(20, 0)
103 #define MT_RXV3_WB_RSSI			GENMASK(31, 24)
106 #define MT_RXV4_RCPI3			GENMASK(31, 24)
109 #define MT_RXV4_RCPI0			GENMASK(7, 0)
111 #define MT_RXV5_FOE			GENMASK(11, 0)
113 #define MT_RXV6_NF3			GENMASK(31, 24)
116 #define MT_RXV6_NF0			GENMASK(7, 0)
138 	MT_TX_MCU_PORT_RX_Q0 = 0,
142 	MT_TX_MCU_PORT_RX_FWDL = 0x1e
152 #define MT_CT_INFO_APPLY_TXD		BIT(0)
164 #define MT_TXD0_P_IDX			BIT(31)
169 #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
171 #define MT_TXD1_OWN_MAC			GENMASK(31, 26)
181 #define MT_TXD1_WLAN_IDX		GENMASK(7, 0)
183 #define MT_TXD2_FIX_RATE		BIT(31)
198 #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
200 #define MT_TXD3_SN_VALID		BIT(31)
206 #define MT_TXD3_NO_ACK			BIT(0)
208 #define MT_TXD4_PN_LOW			GENMASK(31, 0)
210 #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
216 #define MT_TXD5_PID			GENMASK(7, 0)
218 #define MT_TXD6_FIXED_RATE		BIT(31)
226 #define MT_TXD6_BW			GENMASK(1, 0)
228 /* MT7663 DW7 HW-AMSDU */
236 #define MT_TXD8_L_SUB_TYPE		GENMASK(3, 0)
241 #define MT_TX_RATE_IDX			GENMASK(5, 0)
249 #define MT_TXD_LEN_MASK			GENMASK(11, 0)
293 #define MT_TX_FREE_MSDU_ID_CNT		GENMASK(6, 0)
295 #define MT_TXS0_PID			GENMASK(31, 24)
310 #define MT_TXS0_TX_RATE			GENMASK(11, 0)
312 #define MT_TXS1_ANT_ID			GENMASK(31, 20)
320 #define MT_TXS1_TX_POWER_DBM		GENMASK(6, 0)
322 #define MT_TXS2_WCID			GENMASK(31, 24)
324 #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
326 #define MT_TXS3_LAST_TX_RATE		GENMASK(31, 29)
329 #define MT_TXS3_F1_TSSI0		GENMASK(11, 0)
330 #define MT_TXS3_F0_SEQNO		GENMASK(11, 0)
332 #define MT_TXS4_F0_TIMESTAMP		GENMASK(31, 0)
334 #define MT_TXS4_F1_TSSI2		GENMASK(11, 0)
336 #define MT_TXS5_F0_FRONT_TIME		GENMASK(24, 0)
339 #define MT_TXS5_F1_NOISE_0		GENMASK(7, 0)
341 #define MT_TXS6_F1_RCPI_3		GENMASK(31, 24)
344 #define MT_TXS6_F1_RCPI_0		GENMASK(7, 0)