Home
last modified time | relevance | path

Searched +full:0 +full:- +full:3 (Results 1 – 25 of 1062) sorted by relevance

12345678910>>...43

/qemu/include/libdecnumber/
H A DdecDPD.h29 02110-1301, USA. */
31 /* ------------------------------------------------------------------------ */
33 /* [Automatically generated -- do not edit. 2007.05.05] */
34 /* ------------------------------------------------------------------------ */
35 /* ------------------------------------------------------------------------ */
41 /* uint16_t BCD2DPD[2458]; -- BCD -> DPD (0x999 => 2457) */
42 /* uint16_t BIN2DPD[1000]; -- Bin -> DPD (999 => 2457) */
43 /* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
44 /* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
45 /* uint16_t DPD2BCD[1024]; -- DPD -> BCD (0x3FF => 0x999) */
[all …]
H A DdecNumberLocal.h29 02110-1301, USA. */
31 /* ------------------------------------------------------------------ */
33 /* ------------------------------------------------------------------ */
38 /* ------------------------------------------------------------------ */
49 /* Conditional code flag -- set this to match hardware platform */
50 /* 1=little-endian, 0=big-endian */
52 #define DECLITEND 0
57 /* Conditional code flag -- set this to 1 for best performance */
58 #define DECUSE64 1 /* 1=use int64s, 0=int32 & smaller only */
60 /* Conditional check flags -- set these to 0 for best performance */
[all …]
/qemu/disas/
H A Dsparc.c3 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
30 #include "disas/dis-asm.h"
33 the opcodes library in sparc-opc.c. If you change anything here, make
36 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
43 returns non-zero.
44 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
45 Don't change this without updating sparc-opc.c. */
49 SPARC_OPCODE_ARCH_V6 = 0,
62 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
68 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
[all …]
H A Dnanomips.c31 #include "disas/dis-asm.h"
62 return g_strdup_printf("0x%" PRIx64, a); in to_string()
68 return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size); in extract_bits()
74 uint64 shift = 63 - msb; in sign_extend()
86 info->fprintf_func(info->stream, "Invalid register mapping index %" PRIu64 in renumber_registers()
88 siglongjmp(info->buf, 1); in renumber_registers()
93 * decode_gpr_gpr4() - decoder for 'gpr4' gpr encoding type
95 * Map a 4-bit code to the 5-bit register space according to this pattern:
97 * 1 0
98 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
[all …]
/qemu/target/arm/tcg/
H A Dt16.decode42 # Data-processing (two low registers)
44 %reg_0 0:3
46 @lll_noshr ...... .... rm:3 rd:3 \
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
48 @xll_noshr ...... .... rm:3 rn:3 \
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
50 @lxl_shr ...... .... rs:3 rd:3 \
51 &s_rrr_shr %s rm=%reg_0 rn=0
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
[all …]
H A Dneon-dp.decode1 # AArch32 Neon data-processing instruction descriptions
22 %vm_dp 5:1 0:4
29 # 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
31 # 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
36 # 3-reg-same grouping:
37 # 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
40 &3same vm vn vd q size
42 @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
43 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
45 @3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
[all …]
H A Dcrypto_helper.c2 * crypto_helper.c - emulate v8 Crypto Extensions instructions
4 * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
15 #include "tcg/tcg-gvec-desc.h"
16 #include "crypto/aes-round.h"
21 #include "exec/helper-proto.h.inc"
30 #define CR_ST_BYTE(state, i) ((state).bytes[(15 - (i)) ^ 8])
31 #define CR_ST_WORD(state, i) ((state).words[(3 - (i)) ^ 2])
56 for (i = 0; i < opr_sz; i += 16) { in HELPER()
63 * Our uint64_t are in the wrong order for big-endian. in HELPER()
68 t.d[0] = st->d[1] ^ rk->d[1]; in HELPER()
[all …]
/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c33 #include "hw/qdev-properties.h"
34 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
37 #define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0
40 REG32(MIO_PIN_0, 0x0)
41 FIELD(MIO_PIN_0, L3_SEL, 7, 3)
43 FIELD(MIO_PIN_0, L1_SEL, 3, 2)
45 REG32(MIO_PIN_1, 0x4)
46 FIELD(MIO_PIN_1, L3_SEL, 7, 3)
48 FIELD(MIO_PIN_1, L1_SEL, 3, 2)
50 REG32(MIO_PIN_2, 0x8)
[all …]
/qemu/target/arm/hvf/
H A Dhvf.c8 * See the COPYING file in the top-level directory.
13 #include "qemu/error-report.h"
25 #include "system/address-spaces.h"
29 #include "qemu/main-loop.h"
31 #include "arm-powerctl.h"
41 #define MDSCR_EL1_SS_SHIFT 0
158 #define SYSREG_OP0_MASK 0x3
161 #define SYSREG_OP1_MASK 0x7
164 #define SYSREG_CRN_MASK 0xf
167 #define SYSREG_CRM_MASK 0xf
[all …]
/qemu/linux-headers/asm-arm64/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
26 #define KVM_SPSR_EL1 0
30 #define KVM_SPSR_IRQ 3
58 * Supported CPU Targets - Adding a new target type is not recommended,
62 #define KVM_ARM_TARGET_AEM_V8 0
65 #define KVM_ARM_TARGET_XGENE_POTENZA 3
73 #define KVM_ARM_DEVICE_TYPE_SHIFT 0
81 #define KVM_ARM_DEVICE_VGIC_V2 0
[all …]
/qemu/include/hw/misc/
H A Dxlnx-versal-crl.h2 * QEMU model of the Clock-Reset-LPD (CRL).
5 * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "target/arm/cpu-qom.h"
16 #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
19 REG32(ERR_CTRL, 0x0)
20 FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
21 REG32(IR_STATUS, 0x4)
22 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
23 REG32(IR_MASK, 0x8)
24 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
[all …]
H A Dxlnx-zynqmp-crf.h2 * QEMU model of the CRF - Clock Reset FPD.
5 * SPDX-License-Identifier: GPL-2.0-or-later
17 REG32(ERR_CTRL, 0x0)
18 FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
19 REG32(IR_STATUS, 0x4)
20 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
21 REG32(IR_MASK, 0x8)
22 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
23 REG32(IR_ENABLE, 0xc)
24 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
[all …]
/qemu/tests/unit/
H A Dtest-fifo.c4 * Copyright 2024 Mark Cave-Ayland
7 * Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
10 * See the COPYING.LIB file in the top-level directory.
24 uint8_t data_in1[] = { 0x1, 0x2, 0x3, 0x4 }; in test_fifo8_pop_bufptr_wrap()
25 uint8_t data_in2[] = { 0x5, 0x6, 0x7, 0x8, 0x9, 0xa }; in test_fifo8_pop_bufptr_wrap()
31 * head --v-- tail used = 0 in test_fifo8_pop_bufptr_wrap()
37 * head --v ]-- tail used = 4 in test_fifo8_pop_bufptr_wrap()
38 * FIFO: [ 1 2 3 4 . . . . ] in test_fifo8_pop_bufptr_wrap()
42 * head --v ]-- tail used = 2 in test_fifo8_pop_bufptr_wrap()
43 * FIFO: [ 1 2 3 4 . . . . ] in test_fifo8_pop_bufptr_wrap()
[all …]
/qemu/target/xtensa/
H A Dxtensa-semi.c30 #include "chardev/char-fe.h"
31 #include "exec/helper-proto.h"
40 TARGET_SYS_read = 3,
56 SELECT_ONE_EXCEPT = 3,
62 TARGET_ESRCH = 3,
101 case 0: return 0; in errno_h2g()
164 return sizeof(p->input.buffer) - p->input.offset; in sim_console_can_read()
171 size_t copy = sizeof(p->input.buffer) - p->input.offset; in sim_console_read()
176 memcpy(p->input.buffer + p->input.offset, buf, copy); in sim_console_read()
177 p->input.offset += copy; in sim_console_read()
[all …]
/qemu/hw/sparc64/
H A Dsun4u_iommu.c6 * Copyright (c) 2017 Mark Cave-Ayland
30 #include "system/address-spaces.h"
37 #define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1))
39 #define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1))
41 #define IOMMU_CTRL 0x0
47 #define IOMMU_BASE 0x8
48 #define IOMMU_FLUSH 0x10
54 #define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL
55 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
57 #define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
[all …]
/qemu/docs/specs/
H A Dppc-spapr-numa.rst12 --------------------------------------------
19 bit 0 of byte 5 of the ibm,architecture-vec-5 property. The format with
20 bit 0 equal to zero is deprecated. The current format, with the bit 0
28 Mem M1 ---- Proc P1 |
29 ----------------- | Socket S1 ---|
32 Mem M2 ---- Proc P2 | |
33 ----------------- | Socket S2 ---|
46 Relative Performance Distance and ibm,associativity-reference-points
47 --------------------------------------------------------------------
49 The ibm,associativity-reference-points property is an array that is used
[all …]
/qemu/tests/tcg/s390x/
H A Dsam.S1 /* DAT on, home-space mode, 64-bit mode */
2 #define DAT_PSWM 0x400c00180000000
3 #define VIRTUAL_BASE 0x123456789abcd000
5 .org 0x8e
7 .org 0x150
9 .org 0x1d0 /* program new PSW */
10 .quad 0,pgm_handler
11 .org 0x200 /* lowcore padding */
23 lpswe failure_psw-.(%r12)
37 .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
[all …]
H A Dlcbb.c4 * SPDX-License-Identifier: GPL-2.0-or-later
17 *cc = (*cc >> 28) & 3; in lcbb()
20 static char buf[0x1000] __attribute__((aligned(0x1000)));
25 long r1 = 0xfedcba9876543210; in test_lcbb()
29 assert(r1 == (0xfedcba9800000000 | exp_r1)); in test_lcbb()
35 test_lcbb(&buf[0], 0, 16, 0); in main()
36 test_lcbb(&buf[63], 0, 1, 3); in main()
37 test_lcbb(&buf[0], 1, 16, 0); in main()
38 test_lcbb(&buf[127], 1, 1, 3); in main()
39 test_lcbb(&buf[0], 2, 16, 0); in main()
[all …]
/qemu/target/arm/
H A Dhelper.c6 * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cpu-features.h"
15 #include "exec/page-protection.h"
16 #include "exec/mmap-lock.h"
17 #include "qemu/main-loop.h"
20 #include "qemu/qemu-print.h"
22 #include "exec/translation-block.h"
24 #include "system/cpu-timers.h"
29 #include "qemu/guest-random.h"
33 #include "semihosting/common-semi.h"
[all …]
H A Dcortex-regs.c2 * ARM Cortex-A registers
6 * SPDX-License-Identifier: GPL-2.0-or-later
23 * all you can report in this two-bit field. Saturate to in l2ctlr_read()
24 * 0b11 (== 4 CPUs) rather than overflowing the field. in l2ctlr_read()
26 return MIN(cpu->core_count - 1, 3) << 24; in l2ctlr_read()
31 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
35 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
39 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
40 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
[all …]
/qemu/hw/display/
H A Dvga-helpers.h28 ((uint32_t *)d)[0] = (-((font_data >> 7)) & xorcol) ^ bgcol; in vga_draw_glyph_line()
29 ((uint32_t *)d)[1] = (-((font_data >> 6) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
30 ((uint32_t *)d)[2] = (-((font_data >> 5) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
31 ((uint32_t *)d)[3] = (-((font_data >> 4) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
32 ((uint32_t *)d)[4] = (-((font_data >> 3) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
33 ((uint32_t *)d)[5] = (-((font_data >> 2) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
34 ((uint32_t *)d)[6] = (-((font_data >> 1) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
35 ((uint32_t *)d)[7] = (-((font_data >> 0) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
46 font_data = font_ptr[0]; in vga_draw_glyph8()
50 } while (--h); in vga_draw_glyph8()
[all …]
/qemu/tests/qemu-iotests/
H A D1224 # Test some qemu-img convert cases
25 seq="$(basename $0)"
37 trap "_cleanup; exit \$status" 0 1 2 3 15
49 $QEMU_IO -c "write -P 0x11 0 64M" "$TEST_IMG".base 2>&1 | _filter_qemu_io | _filter_testdir
53 echo "=== Check allocation status regression with -B ==="
56 _make_test_img -b "$TEST_IMG".base -F $IMGFMT
57 $QEMU_IO -c "write -P 0x22 0 3M" "$TEST_IMG" 2>&1 | _filter_qemu_io | _filter_testdir
58 $QEMU_IMG convert -O $IMGFMT -B "$TEST_IMG".base \
59 -o backing_fmt=$IMGFMT "$TEST_IMG" "$TEST_IMG".orig
67 _make_test_img -b "$TEST_IMG".base -F $IMGFMT
[all …]
/qemu/rust/qemu-api/tests/
H A Dvmstate_tests.rs3 // SPDX-License-Identifier: GPL-2.0-or-later
24 const FOO_ARRAY_MAX: usize = 3;
30 // - VMSTATE_U16
31 // - VMSTATE_UNUSED
32 // - VMSTATE_VARRAY_UINT16_UNSAFE
33 // - VMSTATE_VARRAY_MULTIPLY
51 vmstate_of!(FooA, arr[0 .. num]).with_version_id(0),
52 vmstate_of!(FooA, arr_mul[0 .. num_mul * 16]),
63 unsafe { CStr::from_ptr(foo_fields[0].name) }.to_bytes_with_nul(), in test_vmstate_uint16()
64 b"elem\0" in test_vmstate_uint16()
[all …]
/qemu/host/include/loongarch64/host/
H A Dbufferiszero.c.inc2 * SPDX-License-Identifier: GPL-2.0-or-later
16 const void *e = QEMU_ALIGN_PTR_DOWN(buf + len - 1, 16) - (7 * 16);
20 asm("vld $vr0,%2,0\n\t" /* first: buf + 0 */
21 "vld $vr1,%4,-16\n\t" /* last: buf + len - 16 */
22 "vld $vr2,%3,0\n\t" /* e[0] */
23 "vld $vr3,%3,16\n\t" /* e[1] */
24 "vld $vr4,%3,32\n\t" /* e[2] */
25 "vld $vr5,%3,48\n\t" /* e[3] */
26 "vld $vr6,%3,64\n\t" /* e[4] */
27 "vld $vr7,%3,80\n\t" /* e[5] */
[all …]
/qemu/hw/net/can/
H A Dcan_sja1000.c2 * CAN device - SJA1000 chip emulation for QEMU
4 * Copyright (c) 2013-2014 Jin Yang
5 * Copyright (c) 2014-2018 Pavel Pisa
38 #define DEBUG_FILTER 0
42 #define DEBUG_CAN 0
50 } while (0)
54 s->mode &= ~0x31; in can_sja_software_reset()
55 s->mode |= 0x01; in can_sja_software_reset()
56 s->status_pel &= ~0x37; in can_sja_software_reset()
57 s->status_pel |= 0x34; in can_sja_software_reset()
[all …]

12345678910>>...43