Lines Matching +full:0 +full:- +full:3
33 #include "hw/qdev-properties.h"
34 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
37 #define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0
40 REG32(MIO_PIN_0, 0x0)
41 FIELD(MIO_PIN_0, L3_SEL, 7, 3)
43 FIELD(MIO_PIN_0, L1_SEL, 3, 2)
45 REG32(MIO_PIN_1, 0x4)
46 FIELD(MIO_PIN_1, L3_SEL, 7, 3)
48 FIELD(MIO_PIN_1, L1_SEL, 3, 2)
50 REG32(MIO_PIN_2, 0x8)
51 FIELD(MIO_PIN_2, L3_SEL, 7, 3)
53 FIELD(MIO_PIN_2, L1_SEL, 3, 2)
55 REG32(MIO_PIN_3, 0xc)
56 FIELD(MIO_PIN_3, L3_SEL, 7, 3)
58 FIELD(MIO_PIN_3, L1_SEL, 3, 2)
60 REG32(MIO_PIN_4, 0x10)
61 FIELD(MIO_PIN_4, L3_SEL, 7, 3)
63 FIELD(MIO_PIN_4, L1_SEL, 3, 2)
65 REG32(MIO_PIN_5, 0x14)
66 FIELD(MIO_PIN_5, L3_SEL, 7, 3)
68 FIELD(MIO_PIN_5, L1_SEL, 3, 2)
70 REG32(MIO_PIN_6, 0x18)
71 FIELD(MIO_PIN_6, L3_SEL, 7, 3)
73 FIELD(MIO_PIN_6, L1_SEL, 3, 2)
75 REG32(MIO_PIN_7, 0x1c)
76 FIELD(MIO_PIN_7, L3_SEL, 7, 3)
78 FIELD(MIO_PIN_7, L1_SEL, 3, 2)
80 REG32(MIO_PIN_8, 0x20)
81 FIELD(MIO_PIN_8, L3_SEL, 7, 3)
83 FIELD(MIO_PIN_8, L1_SEL, 3, 2)
85 REG32(MIO_PIN_9, 0x24)
86 FIELD(MIO_PIN_9, L3_SEL, 7, 3)
88 FIELD(MIO_PIN_9, L1_SEL, 3, 2)
90 REG32(MIO_PIN_10, 0x28)
91 FIELD(MIO_PIN_10, L3_SEL, 7, 3)
93 FIELD(MIO_PIN_10, L1_SEL, 3, 2)
95 REG32(MIO_PIN_11, 0x2c)
96 FIELD(MIO_PIN_11, L3_SEL, 7, 3)
98 FIELD(MIO_PIN_11, L1_SEL, 3, 2)
100 REG32(MIO_PIN_12, 0x30)
101 FIELD(MIO_PIN_12, L3_SEL, 7, 3)
103 FIELD(MIO_PIN_12, L1_SEL, 3, 2)
105 REG32(MIO_PIN_13, 0x34)
106 FIELD(MIO_PIN_13, L3_SEL, 7, 3)
108 FIELD(MIO_PIN_13, L1_SEL, 3, 2)
110 REG32(MIO_PIN_14, 0x38)
111 FIELD(MIO_PIN_14, L3_SEL, 7, 3)
113 FIELD(MIO_PIN_14, L1_SEL, 3, 2)
115 REG32(MIO_PIN_15, 0x3c)
116 FIELD(MIO_PIN_15, L3_SEL, 7, 3)
118 FIELD(MIO_PIN_15, L1_SEL, 3, 2)
120 REG32(MIO_PIN_16, 0x40)
121 FIELD(MIO_PIN_16, L3_SEL, 7, 3)
123 FIELD(MIO_PIN_16, L1_SEL, 3, 2)
125 REG32(MIO_PIN_17, 0x44)
126 FIELD(MIO_PIN_17, L3_SEL, 7, 3)
128 FIELD(MIO_PIN_17, L1_SEL, 3, 2)
130 REG32(MIO_PIN_18, 0x48)
131 FIELD(MIO_PIN_18, L3_SEL, 7, 3)
133 FIELD(MIO_PIN_18, L1_SEL, 3, 2)
135 REG32(MIO_PIN_19, 0x4c)
136 FIELD(MIO_PIN_19, L3_SEL, 7, 3)
138 FIELD(MIO_PIN_19, L1_SEL, 3, 2)
140 REG32(MIO_PIN_20, 0x50)
141 FIELD(MIO_PIN_20, L3_SEL, 7, 3)
143 FIELD(MIO_PIN_20, L1_SEL, 3, 2)
145 REG32(MIO_PIN_21, 0x54)
146 FIELD(MIO_PIN_21, L3_SEL, 7, 3)
148 FIELD(MIO_PIN_21, L1_SEL, 3, 2)
150 REG32(MIO_PIN_22, 0x58)
151 FIELD(MIO_PIN_22, L3_SEL, 7, 3)
153 FIELD(MIO_PIN_22, L1_SEL, 3, 2)
155 REG32(MIO_PIN_23, 0x5c)
156 FIELD(MIO_PIN_23, L3_SEL, 7, 3)
158 FIELD(MIO_PIN_23, L1_SEL, 3, 2)
160 REG32(MIO_PIN_24, 0x60)
161 FIELD(MIO_PIN_24, L3_SEL, 7, 3)
163 FIELD(MIO_PIN_24, L1_SEL, 3, 2)
165 REG32(MIO_PIN_25, 0x64)
166 FIELD(MIO_PIN_25, L3_SEL, 7, 3)
168 FIELD(MIO_PIN_25, L1_SEL, 3, 2)
170 REG32(MIO_PIN_26, 0x68)
171 FIELD(MIO_PIN_26, L3_SEL, 7, 3)
173 FIELD(MIO_PIN_26, L1_SEL, 3, 2)
175 REG32(MIO_PIN_27, 0x6c)
176 FIELD(MIO_PIN_27, L3_SEL, 7, 3)
178 FIELD(MIO_PIN_27, L1_SEL, 3, 2)
180 REG32(MIO_PIN_28, 0x70)
181 FIELD(MIO_PIN_28, L3_SEL, 7, 3)
183 FIELD(MIO_PIN_28, L1_SEL, 3, 2)
185 REG32(MIO_PIN_29, 0x74)
186 FIELD(MIO_PIN_29, L3_SEL, 7, 3)
188 FIELD(MIO_PIN_29, L1_SEL, 3, 2)
190 REG32(MIO_PIN_30, 0x78)
191 FIELD(MIO_PIN_30, L3_SEL, 7, 3)
193 FIELD(MIO_PIN_30, L1_SEL, 3, 2)
195 REG32(MIO_PIN_31, 0x7c)
196 FIELD(MIO_PIN_31, L3_SEL, 7, 3)
198 FIELD(MIO_PIN_31, L1_SEL, 3, 2)
200 REG32(MIO_PIN_32, 0x80)
201 FIELD(MIO_PIN_32, L3_SEL, 7, 3)
203 FIELD(MIO_PIN_32, L1_SEL, 3, 2)
205 REG32(MIO_PIN_33, 0x84)
206 FIELD(MIO_PIN_33, L3_SEL, 7, 3)
208 FIELD(MIO_PIN_33, L1_SEL, 3, 2)
210 REG32(MIO_PIN_34, 0x88)
211 FIELD(MIO_PIN_34, L3_SEL, 7, 3)
213 FIELD(MIO_PIN_34, L1_SEL, 3, 2)
215 REG32(MIO_PIN_35, 0x8c)
216 FIELD(MIO_PIN_35, L3_SEL, 7, 3)
218 FIELD(MIO_PIN_35, L1_SEL, 3, 2)
220 REG32(MIO_PIN_36, 0x90)
221 FIELD(MIO_PIN_36, L3_SEL, 7, 3)
223 FIELD(MIO_PIN_36, L1_SEL, 3, 2)
225 REG32(MIO_PIN_37, 0x94)
226 FIELD(MIO_PIN_37, L3_SEL, 7, 3)
228 FIELD(MIO_PIN_37, L1_SEL, 3, 2)
230 REG32(MIO_PIN_38, 0x98)
231 FIELD(MIO_PIN_38, L3_SEL, 7, 3)
233 FIELD(MIO_PIN_38, L1_SEL, 3, 2)
235 REG32(MIO_PIN_39, 0x9c)
236 FIELD(MIO_PIN_39, L3_SEL, 7, 3)
238 FIELD(MIO_PIN_39, L1_SEL, 3, 2)
240 REG32(MIO_PIN_40, 0xa0)
241 FIELD(MIO_PIN_40, L3_SEL, 7, 3)
243 FIELD(MIO_PIN_40, L1_SEL, 3, 2)
245 REG32(MIO_PIN_41, 0xa4)
246 FIELD(MIO_PIN_41, L3_SEL, 7, 3)
248 FIELD(MIO_PIN_41, L1_SEL, 3, 2)
250 REG32(MIO_PIN_42, 0xa8)
251 FIELD(MIO_PIN_42, L3_SEL, 7, 3)
253 FIELD(MIO_PIN_42, L1_SEL, 3, 2)
255 REG32(MIO_PIN_43, 0xac)
256 FIELD(MIO_PIN_43, L3_SEL, 7, 3)
258 FIELD(MIO_PIN_43, L1_SEL, 3, 2)
260 REG32(MIO_PIN_44, 0xb0)
261 FIELD(MIO_PIN_44, L3_SEL, 7, 3)
263 FIELD(MIO_PIN_44, L1_SEL, 3, 2)
265 REG32(MIO_PIN_45, 0xb4)
266 FIELD(MIO_PIN_45, L3_SEL, 7, 3)
268 FIELD(MIO_PIN_45, L1_SEL, 3, 2)
270 REG32(MIO_PIN_46, 0xb8)
271 FIELD(MIO_PIN_46, L3_SEL, 7, 3)
273 FIELD(MIO_PIN_46, L1_SEL, 3, 2)
275 REG32(MIO_PIN_47, 0xbc)
276 FIELD(MIO_PIN_47, L3_SEL, 7, 3)
278 FIELD(MIO_PIN_47, L1_SEL, 3, 2)
280 REG32(MIO_PIN_48, 0xc0)
281 FIELD(MIO_PIN_48, L3_SEL, 7, 3)
283 FIELD(MIO_PIN_48, L1_SEL, 3, 2)
285 REG32(MIO_PIN_49, 0xc4)
286 FIELD(MIO_PIN_49, L3_SEL, 7, 3)
288 FIELD(MIO_PIN_49, L1_SEL, 3, 2)
290 REG32(MIO_PIN_50, 0xc8)
291 FIELD(MIO_PIN_50, L3_SEL, 7, 3)
293 FIELD(MIO_PIN_50, L1_SEL, 3, 2)
295 REG32(MIO_PIN_51, 0xcc)
296 FIELD(MIO_PIN_51, L3_SEL, 7, 3)
298 FIELD(MIO_PIN_51, L1_SEL, 3, 2)
300 REG32(BNK0_EN_RX, 0x100)
301 FIELD(BNK0_EN_RX, BNK0_EN_RX, 0, 26)
302 REG32(BNK0_SEL_RX0, 0x104)
303 REG32(BNK0_SEL_RX1, 0x108)
304 FIELD(BNK0_SEL_RX1, BNK0_SEL_RX, 0, 20)
305 REG32(BNK0_EN_RX_SCHMITT_HYST, 0x10c)
306 FIELD(BNK0_EN_RX_SCHMITT_HYST, BNK0_EN_RX_SCHMITT_HYST, 0, 26)
307 REG32(BNK0_EN_WK_PD, 0x110)
308 FIELD(BNK0_EN_WK_PD, BNK0_EN_WK_PD, 0, 26)
309 REG32(BNK0_EN_WK_PU, 0x114)
310 FIELD(BNK0_EN_WK_PU, BNK0_EN_WK_PU, 0, 26)
311 REG32(BNK0_SEL_DRV0, 0x118)
312 REG32(BNK0_SEL_DRV1, 0x11c)
313 FIELD(BNK0_SEL_DRV1, BNK0_SEL_DRV, 0, 20)
314 REG32(BNK0_SEL_SLEW, 0x120)
315 FIELD(BNK0_SEL_SLEW, BNK0_SEL_SLEW, 0, 26)
316 REG32(BNK0_EN_DFT_OPT_INV, 0x124)
317 FIELD(BNK0_EN_DFT_OPT_INV, BNK0_EN_DFT_OPT_INV, 0, 26)
318 REG32(BNK0_EN_PAD2PAD_LOOPBACK, 0x128)
319 FIELD(BNK0_EN_PAD2PAD_LOOPBACK, BNK0_EN_PAD2PAD_LOOPBACK, 0, 13)
320 REG32(BNK0_RX_SPARE0, 0x12c)
321 REG32(BNK0_RX_SPARE1, 0x130)
322 FIELD(BNK0_RX_SPARE1, BNK0_RX_SPARE, 0, 20)
323 REG32(BNK0_TX_SPARE0, 0x134)
324 REG32(BNK0_TX_SPARE1, 0x138)
325 FIELD(BNK0_TX_SPARE1, BNK0_TX_SPARE, 0, 20)
326 REG32(BNK0_SEL_EN1P8, 0x13c)
327 FIELD(BNK0_SEL_EN1P8, BNK0_SEL_EN1P8, 0, 1)
328 REG32(BNK0_EN_B_POR_DETECT, 0x140)
329 FIELD(BNK0_EN_B_POR_DETECT, BNK0_EN_B_POR_DETECT, 0, 1)
330 REG32(BNK0_LPF_BYP_POR_DETECT, 0x144)
331 FIELD(BNK0_LPF_BYP_POR_DETECT, BNK0_LPF_BYP_POR_DETECT, 0, 1)
332 REG32(BNK0_EN_LATCH, 0x148)
333 FIELD(BNK0_EN_LATCH, BNK0_EN_LATCH, 0, 1)
334 REG32(BNK0_VBG_LPF_BYP_B, 0x14c)
335 FIELD(BNK0_VBG_LPF_BYP_B, BNK0_VBG_LPF_BYP_B, 0, 1)
336 REG32(BNK0_EN_AMP_B, 0x150)
337 FIELD(BNK0_EN_AMP_B, BNK0_EN_AMP_B, 0, 2)
338 REG32(BNK0_SPARE_BIAS, 0x154)
339 FIELD(BNK0_SPARE_BIAS, BNK0_SPARE_BIAS, 0, 4)
340 REG32(BNK0_DRIVER_BIAS, 0x158)
341 FIELD(BNK0_DRIVER_BIAS, BNK0_DRIVER_BIAS, 0, 15)
342 REG32(BNK0_VMODE, 0x15c)
343 FIELD(BNK0_VMODE, BNK0_VMODE, 0, 1)
344 REG32(BNK0_SEL_AUX_IO_RX, 0x160)
345 FIELD(BNK0_SEL_AUX_IO_RX, BNK0_SEL_AUX_IO_RX, 0, 26)
346 REG32(BNK0_EN_TX_HS_MODE, 0x164)
347 FIELD(BNK0_EN_TX_HS_MODE, BNK0_EN_TX_HS_MODE, 0, 26)
348 REG32(MIO_MST_TRI0, 0x200)
371 FIELD(MIO_MST_TRI0, PIN_03_TRI, 3, 1)
374 FIELD(MIO_MST_TRI0, PIN_00_TRI, 0, 1)
375 REG32(MIO_MST_TRI1, 0x204)
398 FIELD(MIO_MST_TRI1, PIN_29_TRI, 3, 1)
401 FIELD(MIO_MST_TRI1, PIN_26_TRI, 0, 1)
402 REG32(BNK1_EN_RX, 0x300)
403 FIELD(BNK1_EN_RX, BNK1_EN_RX, 0, 26)
404 REG32(BNK1_SEL_RX0, 0x304)
405 REG32(BNK1_SEL_RX1, 0x308)
406 FIELD(BNK1_SEL_RX1, BNK1_SEL_RX, 0, 20)
407 REG32(BNK1_EN_RX_SCHMITT_HYST, 0x30c)
408 FIELD(BNK1_EN_RX_SCHMITT_HYST, BNK1_EN_RX_SCHMITT_HYST, 0, 26)
409 REG32(BNK1_EN_WK_PD, 0x310)
410 FIELD(BNK1_EN_WK_PD, BNK1_EN_WK_PD, 0, 26)
411 REG32(BNK1_EN_WK_PU, 0x314)
412 FIELD(BNK1_EN_WK_PU, BNK1_EN_WK_PU, 0, 26)
413 REG32(BNK1_SEL_DRV0, 0x318)
414 REG32(BNK1_SEL_DRV1, 0x31c)
415 FIELD(BNK1_SEL_DRV1, BNK1_SEL_DRV, 0, 20)
416 REG32(BNK1_SEL_SLEW, 0x320)
417 FIELD(BNK1_SEL_SLEW, BNK1_SEL_SLEW, 0, 26)
418 REG32(BNK1_EN_DFT_OPT_INV, 0x324)
419 FIELD(BNK1_EN_DFT_OPT_INV, BNK1_EN_DFT_OPT_INV, 0, 26)
420 REG32(BNK1_EN_PAD2PAD_LOOPBACK, 0x328)
421 FIELD(BNK1_EN_PAD2PAD_LOOPBACK, BNK1_EN_PAD2PAD_LOOPBACK, 0, 13)
422 REG32(BNK1_RX_SPARE0, 0x32c)
423 REG32(BNK1_RX_SPARE1, 0x330)
424 FIELD(BNK1_RX_SPARE1, BNK1_RX_SPARE, 0, 20)
425 REG32(BNK1_TX_SPARE0, 0x334)
426 REG32(BNK1_TX_SPARE1, 0x338)
427 FIELD(BNK1_TX_SPARE1, BNK1_TX_SPARE, 0, 20)
428 REG32(BNK1_SEL_EN1P8, 0x33c)
429 FIELD(BNK1_SEL_EN1P8, BNK1_SEL_EN1P8, 0, 1)
430 REG32(BNK1_EN_B_POR_DETECT, 0x340)
431 FIELD(BNK1_EN_B_POR_DETECT, BNK1_EN_B_POR_DETECT, 0, 1)
432 REG32(BNK1_LPF_BYP_POR_DETECT, 0x344)
433 FIELD(BNK1_LPF_BYP_POR_DETECT, BNK1_LPF_BYP_POR_DETECT, 0, 1)
434 REG32(BNK1_EN_LATCH, 0x348)
435 FIELD(BNK1_EN_LATCH, BNK1_EN_LATCH, 0, 1)
436 REG32(BNK1_VBG_LPF_BYP_B, 0x34c)
437 FIELD(BNK1_VBG_LPF_BYP_B, BNK1_VBG_LPF_BYP_B, 0, 1)
438 REG32(BNK1_EN_AMP_B, 0x350)
439 FIELD(BNK1_EN_AMP_B, BNK1_EN_AMP_B, 0, 2)
440 REG32(BNK1_SPARE_BIAS, 0x354)
441 FIELD(BNK1_SPARE_BIAS, BNK1_SPARE_BIAS, 0, 4)
442 REG32(BNK1_DRIVER_BIAS, 0x358)
443 FIELD(BNK1_DRIVER_BIAS, BNK1_DRIVER_BIAS, 0, 15)
444 REG32(BNK1_VMODE, 0x35c)
445 FIELD(BNK1_VMODE, BNK1_VMODE, 0, 1)
446 REG32(BNK1_SEL_AUX_IO_RX, 0x360)
447 FIELD(BNK1_SEL_AUX_IO_RX, BNK1_SEL_AUX_IO_RX, 0, 26)
448 REG32(BNK1_EN_TX_HS_MODE, 0x364)
449 FIELD(BNK1_EN_TX_HS_MODE, BNK1_EN_TX_HS_MODE, 0, 26)
450 REG32(SD0_CLK_CTRL, 0x400)
452 FIELD(SD0_CLK_CTRL, SDIO0_RX_SRC_SEL, 0, 2)
453 REG32(SD0_CTRL_REG, 0x404)
454 FIELD(SD0_CTRL_REG, SD0_EMMC_SEL, 0, 1)
455 REG32(SD0_CONFIG_REG1, 0x410)
458 FIELD(SD0_CONFIG_REG1, SD0_ASYNCWKPENA, 0, 1)
459 REG32(SD0_CONFIG_REG2, 0x414)
469 FIELD(SD0_CONFIG_REG2, SD0_ADMA2, 3, 1)
471 FIELD(SD0_CONFIG_REG2, SD0_MAXBLK, 0, 2)
472 REG32(SD0_CONFIG_REG3, 0x418)
477 FIELD(SD0_CONFIG_REG3, SD0_ADRIVER, 3, 1)
480 FIELD(SD0_CONFIG_REG3, SD0_SDR50, 0, 1)
481 REG32(SD0_INITPRESET, 0x41c)
482 FIELD(SD0_INITPRESET, SD0_INITPRESET, 0, 13)
483 REG32(SD0_DSPPRESET, 0x420)
484 FIELD(SD0_DSPPRESET, SD0_DSPPRESET, 0, 13)
485 REG32(SD0_HSPDPRESET, 0x424)
486 FIELD(SD0_HSPDPRESET, SD0_HSPDPRESET, 0, 13)
487 REG32(SD0_SDR12PRESET, 0x428)
488 FIELD(SD0_SDR12PRESET, SD0_SDR12PRESET, 0, 13)
489 REG32(SD0_SDR25PRESET, 0x42c)
490 FIELD(SD0_SDR25PRESET, SD0_SDR25PRESET, 0, 13)
491 REG32(SD0_SDR50PRSET, 0x430)
492 FIELD(SD0_SDR50PRSET, SD0_SDR50PRESET, 0, 13)
493 REG32(SD0_SDR104PRST, 0x434)
494 FIELD(SD0_SDR104PRST, SD0_SDR104PRESET, 0, 13)
495 REG32(SD0_DDR50PRESET, 0x438)
496 FIELD(SD0_DDR50PRESET, SD0_DDR50PRESET, 0, 13)
497 REG32(SD0_MAXCUR1P8, 0x43c)
498 FIELD(SD0_MAXCUR1P8, SD0_MAXCUR1P8, 0, 8)
499 REG32(SD0_MAXCUR3P0, 0x440)
500 FIELD(SD0_MAXCUR3P0, SD0_MAXCUR3P0, 0, 8)
501 REG32(SD0_MAXCUR3P3, 0x444)
502 FIELD(SD0_MAXCUR3P3, SD0_MAXCUR3P3, 0, 8)
503 REG32(SD0_DLL_CTRL, 0x448)
507 FIELD(SD0_DLL_CTRL, SD0_DLL_OVF, 3, 1)
510 FIELD(SD0_DLL_CTRL, SD0_DLL_LOCK, 0, 1)
511 REG32(SD0_CDN_CTRL, 0x44c)
512 FIELD(SD0_CDN_CTRL, SD0_CDN_CTRL, 0, 1)
513 REG32(SD0_DLL_TEST, 0x450)
516 FIELD(SD0_DLL_TEST, DLL_RX_SEL, 0, 9)
517 REG32(SD0_RX_TUNING_SEL, 0x454)
518 FIELD(SD0_RX_TUNING_SEL, SD0_RX_SEL, 0, 9)
519 REG32(SD0_DLL_DIV_MAP0, 0x458)
523 FIELD(SD0_DLL_DIV_MAP0, DIV_0, 0, 8)
524 REG32(SD0_DLL_DIV_MAP1, 0x45c)
528 FIELD(SD0_DLL_DIV_MAP1, DIV_4, 0, 8)
529 REG32(SD0_IOU_COHERENT_CTRL, 0x460)
530 FIELD(SD0_IOU_COHERENT_CTRL, SD0_AXI_COH, 0, 4)
531 REG32(SD0_IOU_INTERCONNECT_ROUTE, 0x464)
532 FIELD(SD0_IOU_INTERCONNECT_ROUTE, SD0, 0, 1)
533 REG32(SD0_IOU_RAM, 0x468)
535 FIELD(SD0_IOU_RAM, EMAB0, 3, 3)
536 FIELD(SD0_IOU_RAM, EMAA0, 0, 3)
537 REG32(SD0_IOU_INTERCONNECT_QOS, 0x46c)
538 FIELD(SD0_IOU_INTERCONNECT_QOS, SD0_QOS, 0, 4)
539 REG32(SD1_CLK_CTRL, 0x480)
541 FIELD(SD1_CLK_CTRL, SDIO1_RX_SRC_SEL, 0, 1)
542 REG32(SD1_CTRL_REG, 0x484)
543 FIELD(SD1_CTRL_REG, SD1_EMMC_SEL, 0, 1)
544 REG32(SD1_CONFIG_REG1, 0x490)
547 FIELD(SD1_CONFIG_REG1, SD1_ASYNCWKPENA, 0, 1)
548 REG32(SD1_CONFIG_REG2, 0x494)
558 FIELD(SD1_CONFIG_REG2, SD1_ADMA2, 3, 1)
560 FIELD(SD1_CONFIG_REG2, SD1_MAXBLK, 0, 2)
561 REG32(SD1_CONFIG_REG3, 0x498)
566 FIELD(SD1_CONFIG_REG3, SD1_ADRIVER, 3, 1)
569 FIELD(SD1_CONFIG_REG3, SD1_SDR50, 0, 1)
570 REG32(SD1_INITPRESET, 0x49c)
571 FIELD(SD1_INITPRESET, SD1_INITPRESET, 0, 13)
572 REG32(SD1_DSPPRESET, 0x4a0)
573 FIELD(SD1_DSPPRESET, SD1_DSPPRESET, 0, 13)
574 REG32(SD1_HSPDPRESET, 0x4a4)
575 FIELD(SD1_HSPDPRESET, SD1_HSPDPRESET, 0, 13)
576 REG32(SD1_SDR12PRESET, 0x4a8)
577 FIELD(SD1_SDR12PRESET, SD1_SDR12PRESET, 0, 13)
578 REG32(SD1_SDR25PRESET, 0x4ac)
579 FIELD(SD1_SDR25PRESET, SD1_SDR25PRESET, 0, 13)
580 REG32(SD1_SDR50PRSET, 0x4b0)
581 FIELD(SD1_SDR50PRSET, SD1_SDR50PRESET, 0, 13)
582 REG32(SD1_SDR104PRST, 0x4b4)
583 FIELD(SD1_SDR104PRST, SD1_SDR104PRESET, 0, 13)
584 REG32(SD1_DDR50PRESET, 0x4b8)
585 FIELD(SD1_DDR50PRESET, SD1_DDR50PRESET, 0, 13)
586 REG32(SD1_MAXCUR1P8, 0x4bc)
587 FIELD(SD1_MAXCUR1P8, SD1_MAXCUR1P8, 0, 8)
588 REG32(SD1_MAXCUR3P0, 0x4c0)
589 FIELD(SD1_MAXCUR3P0, SD1_MAXCUR3P0, 0, 8)
590 REG32(SD1_MAXCUR3P3, 0x4c4)
591 FIELD(SD1_MAXCUR3P3, SD1_MAXCUR3P3, 0, 8)
592 REG32(SD1_DLL_CTRL, 0x4c8)
596 FIELD(SD1_DLL_CTRL, SD1_DLL_OVF, 3, 1)
599 FIELD(SD1_DLL_CTRL, SD1_DLL_LOCK, 0, 1)
600 REG32(SD1_CDN_CTRL, 0x4cc)
601 FIELD(SD1_CDN_CTRL, SD1_CDN_CTRL, 0, 1)
602 REG32(SD1_DLL_TEST, 0x4d0)
605 FIELD(SD1_DLL_TEST, DLL_RX_SEL, 0, 9)
606 REG32(SD1_RX_TUNING_SEL, 0x4d4)
607 FIELD(SD1_RX_TUNING_SEL, SD1_RX_SEL, 0, 9)
608 REG32(SD1_DLL_DIV_MAP0, 0x4d8)
612 FIELD(SD1_DLL_DIV_MAP0, DIV_0, 0, 8)
613 REG32(SD1_DLL_DIV_MAP1, 0x4dc)
617 FIELD(SD1_DLL_DIV_MAP1, DIV_4, 0, 8)
618 REG32(SD1_IOU_COHERENT_CTRL, 0x4e0)
619 FIELD(SD1_IOU_COHERENT_CTRL, SD1_AXI_COH, 0, 4)
620 REG32(SD1_IOU_INTERCONNECT_ROUTE, 0x4e4)
621 FIELD(SD1_IOU_INTERCONNECT_ROUTE, SD1, 0, 1)
622 REG32(SD1_IOU_RAM, 0x4e8)
624 FIELD(SD1_IOU_RAM, EMAB0, 3, 3)
625 FIELD(SD1_IOU_RAM, EMAA0, 0, 3)
626 REG32(SD1_IOU_INTERCONNECT_QOS, 0x4ec)
627 FIELD(SD1_IOU_INTERCONNECT_QOS, SD1_QOS, 0, 4)
628 REG32(OSPI_QSPI_IOU_AXI_MUX_SEL, 0x504)
630 FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, QSPI_OSPI_MUX_SEL, 0, 1)
631 REG32(QSPI_IOU_COHERENT_CTRL, 0x508)
632 FIELD(QSPI_IOU_COHERENT_CTRL, QSPI_AXI_COH, 0, 4)
633 REG32(QSPI_IOU_INTERCONNECT_ROUTE, 0x50c)
634 FIELD(QSPI_IOU_INTERCONNECT_ROUTE, QSPI, 0, 1)
635 REG32(QSPI_IOU_RAM, 0x510)
637 FIELD(QSPI_IOU_RAM, EMAB1, 10, 3)
638 FIELD(QSPI_IOU_RAM, EMAA1, 7, 3)
640 FIELD(QSPI_IOU_RAM, EMAB0, 3, 3)
641 FIELD(QSPI_IOU_RAM, EMAA0, 0, 3)
642 REG32(QSPI_IOU_INTERCONNECT_QOS, 0x514)
643 FIELD(QSPI_IOU_INTERCONNECT_QOS, QSPI_QOS, 0, 4)
644 REG32(OSPI_IOU_COHERENT_CTRL, 0x530)
645 FIELD(OSPI_IOU_COHERENT_CTRL, OSPI_AXI_COH, 0, 4)
646 REG32(OSPI_IOU_INTERCONNECT_ROUTE, 0x534)
647 FIELD(OSPI_IOU_INTERCONNECT_ROUTE, OSPI, 0, 1)
648 REG32(OSPI_IOU_RAM, 0x538)
650 FIELD(OSPI_IOU_RAM, EMAW0, 3, 2)
651 FIELD(OSPI_IOU_RAM, EMA0, 0, 3)
652 REG32(OSPI_IOU_INTERCONNECT_QOS, 0x53c)
653 FIELD(OSPI_IOU_INTERCONNECT_QOS, OSPI_QOS, 0, 4)
654 REG32(OSPI_REFCLK_DLY_CTRL, 0x540)
655 FIELD(OSPI_REFCLK_DLY_CTRL, DLY1, 3, 2)
656 FIELD(OSPI_REFCLK_DLY_CTRL, DLY0, 0, 3)
657 REG32(CUR_PWR_ST, 0x600)
658 FIELD(CUR_PWR_ST, U2PMU, 0, 2)
659 REG32(CONNECT_ST, 0x604)
660 FIELD(CONNECT_ST, U2PMU, 0, 1)
661 REG32(PW_STATE_REQ, 0x608)
662 FIELD(PW_STATE_REQ, BIT_1_0, 0, 2)
663 REG32(HOST_U2_PORT_DISABLE, 0x60c)
664 FIELD(HOST_U2_PORT_DISABLE, BIT_0, 0, 1)
665 REG32(DBG_U2PMU, 0x610)
666 REG32(DBG_U2PMU_EXT1, 0x614)
667 REG32(DBG_U2PMU_EXT2, 0x618)
668 FIELD(DBG_U2PMU_EXT2, BIT_67_64, 0, 4)
669 REG32(PME_GEN_U2PMU, 0x61c)
670 FIELD(PME_GEN_U2PMU, BIT_0, 0, 1)
671 REG32(PWR_CONFIG_USB2, 0x620)
672 FIELD(PWR_CONFIG_USB2, STRAP, 0, 30)
673 REG32(PHY_HUB, 0x624)
675 FIELD(PHY_HUB, OVER_CURRENT, 0, 1)
676 REG32(CTRL, 0x700)
677 FIELD(CTRL, SLVERR_ENABLE, 0, 1)
678 REG32(ISR, 0x800)
679 FIELD(ISR, ADDR_DECODE_ERR, 0, 1)
680 REG32(IMR, 0x804)
681 FIELD(IMR, ADDR_DECODE_ERR, 0, 1)
682 REG32(IER, 0x808)
683 FIELD(IER, ADDR_DECODE_ERR, 0, 1)
684 REG32(IDR, 0x80c)
685 FIELD(IDR, ADDR_DECODE_ERR, 0, 1)
686 REG32(ITR, 0x810)
687 FIELD(ITR, ADDR_DECODE_ERR, 0, 1)
688 REG32(PARITY_ISR, 0x814)
698 FIELD(PARITY_ISR, PERR_QSPI0_APB, 3, 1)
701 FIELD(PARITY_ISR, PERR_GPIO_APB, 0, 1)
702 REG32(PARITY_IMR, 0x818)
712 FIELD(PARITY_IMR, PERR_QSPI0_APB, 3, 1)
715 FIELD(PARITY_IMR, PERR_GPIO_APB, 0, 1)
716 REG32(PARITY_IER, 0x81c)
726 FIELD(PARITY_IER, PERR_QSPI0_APB, 3, 1)
729 FIELD(PARITY_IER, PERR_GPIO_APB, 0, 1)
730 REG32(PARITY_IDR, 0x820)
740 FIELD(PARITY_IDR, PERR_QSPI0_APB, 3, 1)
743 FIELD(PARITY_IDR, PERR_GPIO_APB, 0, 1)
744 REG32(PARITY_ITR, 0x824)
754 FIELD(PARITY_ITR, PERR_QSPI0_APB, 3, 1)
757 FIELD(PARITY_ITR, PERR_GPIO_APB, 0, 1)
758 REG32(WPROT0, 0x828)
759 FIELD(WPROT0, ACTIVE, 0, 1)
763 bool pending = s->regs[R_PARITY_ISR] & ~s->regs[R_PARITY_IMR]; in parity_imr_update_irq()
764 qemu_set_irq(s->irq_parity_imr, pending); in parity_imr_update_irq()
769 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in parity_isr_postw()
775 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in parity_ier_prew()
778 s->regs[R_PARITY_IMR] &= ~val; in parity_ier_prew()
780 return 0; in parity_ier_prew()
785 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in parity_idr_prew()
788 s->regs[R_PARITY_IMR] |= val; in parity_idr_prew()
790 return 0; in parity_idr_prew()
795 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in parity_itr_prew()
798 s->regs[R_PARITY_ISR] |= val; in parity_itr_prew()
800 return 0; in parity_itr_prew()
805 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR]; in imr_update_irq()
806 qemu_set_irq(s->irq_imr, pending); in imr_update_irq()
811 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in isr_postw()
817 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in ier_prew()
820 s->regs[R_IMR] &= ~val; in ier_prew()
822 return 0; in ier_prew()
827 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in idr_prew()
830 s->regs[R_IMR] |= val; in idr_prew()
832 return 0; in idr_prew()
837 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in itr_prew()
840 s->regs[R_ISR] |= val; in itr_prew()
842 return 0; in itr_prew()
847 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in sd0_ctrl_reg_prew()
848 uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD0_CTRL_REG, SD0_EMMC_SEL); in sd0_ctrl_reg_prew()
851 qemu_set_irq(s->sd_emmc_sel[0], !!val64); in sd0_ctrl_reg_prew()
859 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in sd1_ctrl_reg_prew()
860 uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD1_CTRL_REG, SD1_EMMC_SEL); in sd1_ctrl_reg_prew()
863 qemu_set_irq(s->sd_emmc_sel[1], !!val64); in sd1_ctrl_reg_prew()
872 XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); in ospi_qspi_iou_axi_mux_sel_prew()
880 ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL)) { in ospi_qspi_iou_axi_mux_sel_prew()
881 qemu_set_irq(s->ospi_mux_sel, !!ospi_mux_sel); in ospi_qspi_iou_axi_mux_sel_prew()
885 ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, in ospi_qspi_iou_axi_mux_sel_prew()
887 qemu_set_irq(s->qspi_ospi_mux_sel, !!qspi_ospi_mux_sel); in ospi_qspi_iou_axi_mux_sel_prew()
895 .rsvd = 0xfffffc01,
897 .rsvd = 0xfffffc01,
899 .rsvd = 0xfffffc01,
901 .rsvd = 0xfffffc01,
903 .rsvd = 0xfffffc01,
905 .rsvd = 0xfffffc01,
907 .rsvd = 0xfffffc01,
909 .rsvd = 0xfffffc01,
911 .rsvd = 0xfffffc01,
913 .rsvd = 0xfffffc01,
915 .rsvd = 0xfffffc01,
917 .rsvd = 0xfffffc01,
919 .rsvd = 0xfffffc01,
921 .rsvd = 0xfffffc01,
923 .rsvd = 0xfffffc01,
925 .rsvd = 0xfffffc01,
927 .rsvd = 0xfffffc01,
929 .rsvd = 0xfffffc01,
931 .rsvd = 0xfffffc01,
933 .rsvd = 0xfffffc01,
935 .rsvd = 0xfffffc01,
937 .rsvd = 0xfffffc01,
939 .rsvd = 0xfffffc01,
941 .rsvd = 0xfffffc01,
943 .rsvd = 0xfffffc01,
945 .rsvd = 0xfffffc01,
947 .rsvd = 0xfffffc01,
949 .rsvd = 0xfffffc01,
951 .rsvd = 0xfffffc01,
953 .rsvd = 0xfffffc01,
955 .rsvd = 0xfffffc01,
957 .rsvd = 0xfffffc01,
959 .rsvd = 0xfffffc01,
961 .rsvd = 0xfffffc01,
963 .rsvd = 0xfffffc01,
965 .rsvd = 0xfffffc01,
967 .rsvd = 0xfffffc01,
969 .rsvd = 0xfffffc01,
971 .rsvd = 0xfffffc01,
973 .rsvd = 0xfffffc01,
975 .rsvd = 0xfffffc01,
977 .rsvd = 0xfffffc01,
979 .rsvd = 0xfffffc01,
981 .rsvd = 0xfffffc01,
983 .rsvd = 0xfffffc01,
985 .rsvd = 0xfffffc01,
987 .rsvd = 0xfffffc01,
989 .rsvd = 0xfffffc01,
991 .rsvd = 0xfffffc01,
993 .rsvd = 0xfffffc01,
995 .rsvd = 0xfffffc01,
997 .rsvd = 0xfffffc01,
999 .reset = 0x3ffffff,
1000 .rsvd = 0xfc000000,
1002 .reset = 0xffffffff,
1004 .reset = 0xfffff,
1005 .rsvd = 0xfff00000,
1007 .rsvd = 0xfc000000,
1009 .rsvd = 0xfc000000,
1011 .reset = 0x3ffffff,
1012 .rsvd = 0xfc000000,
1014 .reset = 0xffffffff,
1016 .reset = 0xfffff,
1017 .rsvd = 0xfff00000,
1019 .rsvd = 0xfc000000,
1021 .rsvd = 0xfc000000,
1024 .rsvd = 0xffffe000,
1027 .rsvd = 0xfff00000,
1030 .rsvd = 0xfff00000,
1032 .rsvd = 0xfffffffe,
1034 .rsvd = 0xfffffffe,
1036 .reset = 0x1,
1037 .rsvd = 0xfffffffe,
1039 .rsvd = 0xfffffffe,
1041 .reset = 0x1,
1042 .rsvd = 0xfffffffe,
1044 .rsvd = 0xfffffffc,
1046 .rsvd = 0xfffffff0,
1048 .rsvd = 0xffff8000,
1050 .rsvd = 0xfffffffe,
1051 .ro = 0x1,
1053 .rsvd = 0xfc000000,
1055 .rsvd = 0xfc000000,
1057 .reset = 0x3ffffff,
1058 .rsvd = 0xfc000000,
1060 .reset = 0x3ffffff,
1061 .rsvd = 0xfc000000,
1063 .reset = 0x3ffffff,
1064 .rsvd = 0xfc000000,
1066 .reset = 0xffffffff,
1068 .reset = 0xfffff,
1069 .rsvd = 0xfff00000,
1071 .rsvd = 0xfc000000,
1073 .rsvd = 0xfc000000,
1075 .reset = 0x3ffffff,
1076 .rsvd = 0xfc000000,
1078 .reset = 0xffffffff,
1080 .reset = 0xfffff,
1081 .rsvd = 0xfff00000,
1083 .rsvd = 0xfc000000,
1085 .rsvd = 0xfc000000,
1088 .rsvd = 0xffffe000,
1091 .rsvd = 0xfff00000,
1094 .rsvd = 0xfff00000,
1096 .rsvd = 0xfffffffe,
1098 .rsvd = 0xfffffffe,
1100 .reset = 0x1,
1101 .rsvd = 0xfffffffe,
1103 .rsvd = 0xfffffffe,
1105 .reset = 0x1,
1106 .rsvd = 0xfffffffe,
1108 .rsvd = 0xfffffffc,
1110 .rsvd = 0xfffffff0,
1112 .rsvd = 0xffff8000,
1114 .rsvd = 0xfffffffe,
1115 .ro = 0x1,
1117 .rsvd = 0xfc000000,
1119 .rsvd = 0xfc000000,
1121 .rsvd = 0xfffffff8,
1123 .rsvd = 0xfffffffe,
1126 .reset = 0x3250,
1127 .rsvd = 0xffff8000,
1129 .reset = 0xffc,
1130 .rsvd = 0xffffc000,
1132 .reset = 0x407,
1133 .rsvd = 0xfffff800,
1135 .reset = 0x100,
1136 .rsvd = 0xffffe000,
1138 .reset = 0x4,
1139 .rsvd = 0xffffe000,
1141 .reset = 0x2,
1142 .rsvd = 0xffffe000,
1144 .reset = 0x4,
1145 .rsvd = 0xffffe000,
1147 .reset = 0x2,
1148 .rsvd = 0xffffe000,
1150 .reset = 0x1,
1151 .rsvd = 0xffffe000,
1153 .rsvd = 0xffffe000,
1155 .reset = 0x2,
1156 .rsvd = 0xffffe000,
1158 .rsvd = 0xffffff00,
1160 .rsvd = 0xffffff00,
1162 .rsvd = 0xffffff00,
1164 .reset = 0x1,
1165 .rsvd = 0xfffffc00,
1166 .ro = 0x19,
1168 .rsvd = 0xfffffffe,
1170 .rsvd = 0xff000000,
1172 .rsvd = 0xfffffe00,
1173 .ro = 0x1ff,
1175 .reset = 0x50505050,
1177 .reset = 0x50505050,
1179 .rsvd = 0xfffffff0,
1182 .rsvd = 0xfffffffe,
1184 .reset = 0x24,
1185 .rsvd = 0xffffff80,
1188 .rsvd = 0xfffffff0,
1190 .rsvd = 0xfffffffc,
1192 .rsvd = 0xfffffffe,
1195 .reset = 0x3250,
1196 .rsvd = 0xffff8000,
1198 .reset = 0xffc,
1199 .rsvd = 0xffffc000,
1201 .reset = 0x407,
1202 .rsvd = 0xfffff800,
1204 .reset = 0x100,
1205 .rsvd = 0xffffe000,
1207 .reset = 0x4,
1208 .rsvd = 0xffffe000,
1210 .reset = 0x2,
1211 .rsvd = 0xffffe000,
1213 .reset = 0x4,
1214 .rsvd = 0xffffe000,
1216 .reset = 0x2,
1217 .rsvd = 0xffffe000,
1219 .reset = 0x1,
1220 .rsvd = 0xffffe000,
1222 .rsvd = 0xffffe000,
1224 .reset = 0x2,
1225 .rsvd = 0xffffe000,
1227 .rsvd = 0xffffff00,
1229 .rsvd = 0xffffff00,
1231 .rsvd = 0xffffff00,
1233 .reset = 0x1,
1234 .rsvd = 0xfffffc00,
1235 .ro = 0x19,
1237 .rsvd = 0xfffffffe,
1239 .rsvd = 0xff000000,
1241 .rsvd = 0xfffffe00,
1242 .ro = 0x1ff,
1244 .reset = 0x50505050,
1246 .reset = 0x50505050,
1248 .rsvd = 0xfffffff0,
1251 .rsvd = 0xfffffffe,
1253 .reset = 0x24,
1254 .rsvd = 0xffffff80,
1257 .rsvd = 0xfffffff0,
1260 .reset = 0x1,
1261 .rsvd = 0xfffffffc,
1264 .rsvd = 0xfffffff0,
1267 .rsvd = 0xfffffffe,
1269 .reset = 0x1224,
1270 .rsvd = 0xffffc000,
1273 .rsvd = 0xfffffff0,
1275 .rsvd = 0xfffffff0,
1278 .rsvd = 0xfffffffe,
1280 .reset = 0xa,
1281 .rsvd = 0xffffffc0,
1284 .rsvd = 0xfffffff0,
1286 .reset = 0x13,
1287 .rsvd = 0xffffffe0,
1289 .rsvd = 0xfffffffc,
1290 .ro = 0x3,
1292 .rsvd = 0xfffffffe,
1293 .ro = 0x1,
1295 .rsvd = 0xfffffffc,
1297 .rsvd = 0xfffffffe,
1299 .ro = 0xffffffff,
1301 .ro = 0xffffffff,
1303 .rsvd = 0xfffffff0,
1304 .ro = 0xf,
1306 .rsvd = 0xfffffffe,
1307 .ro = 0x1,
1309 .rsvd = 0xc0000000,
1311 .rsvd = 0xfffffffc,
1312 .ro = 0x2,
1315 .w1c = 0x1,
1318 .reset = 0x1,
1319 .ro = 0x1,
1327 .w1c = 0x1fff,
1330 .reset = 0x1fff,
1331 .ro = 0x1fff,
1339 .reset = 0x1,
1348 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { in xlnx_versal_pmc_iou_slcr_reset_init()
1349 register_reset(&s->regs_info[i]); in xlnx_versal_pmc_iou_slcr_reset_init()
1362 * By default axi slave interface is enabled for ospi-dma in xlnx_versal_pmc_iou_slcr_reset_hold()
1364 qemu_set_irq(s->ospi_mux_sel, 0); in xlnx_versal_pmc_iou_slcr_reset_hold()
1365 qemu_set_irq(s->qspi_ospi_mux_sel, 1); in xlnx_versal_pmc_iou_slcr_reset_hold()
1382 qdev_init_gpio_out_named(dev, s->sd_emmc_sel, "sd-emmc-sel", 2); in xlnx_versal_pmc_iou_slcr_realize()
1383 qdev_init_gpio_out_named(dev, &s->qspi_ospi_mux_sel, in xlnx_versal_pmc_iou_slcr_realize()
1384 "qspi-ospi-mux-sel", 1); in xlnx_versal_pmc_iou_slcr_realize()
1385 qdev_init_gpio_out_named(dev, &s->ospi_mux_sel, "ospi-mux-sel", 1); in xlnx_versal_pmc_iou_slcr_realize()
1394 memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_PMC_IOU_SLCR, in xlnx_versal_pmc_iou_slcr_init()
1399 s->regs_info, s->regs, in xlnx_versal_pmc_iou_slcr_init()
1403 memory_region_add_subregion(&s->iomem, in xlnx_versal_pmc_iou_slcr_init()
1404 0x0, in xlnx_versal_pmc_iou_slcr_init()
1405 ®_array->mem); in xlnx_versal_pmc_iou_slcr_init()
1406 sysbus_init_mmio(sbd, &s->iomem); in xlnx_versal_pmc_iou_slcr_init()
1407 sysbus_init_irq(sbd, &s->irq_parity_imr); in xlnx_versal_pmc_iou_slcr_init()
1408 sysbus_init_irq(sbd, &s->irq_imr); in xlnx_versal_pmc_iou_slcr_init()
1428 dc->realize = xlnx_versal_pmc_iou_slcr_realize; in xlnx_versal_pmc_iou_slcr_class_init()
1429 dc->vmsd = &vmstate_pmc_iou_slcr; in xlnx_versal_pmc_iou_slcr_class_init()
1430 rc->phases.enter = xlnx_versal_pmc_iou_slcr_reset_init; in xlnx_versal_pmc_iou_slcr_class_init()
1431 rc->phases.hold = xlnx_versal_pmc_iou_slcr_reset_hold; in xlnx_versal_pmc_iou_slcr_class_init()